* iothread bugfix (Eduardo)
* Linux headers sync (Dave) * .gitignore fix (Eric) * KVM capability check fixes (Greg) * kvmclock fix (Jim) -----BEGIN PGP SIGNATURE----- iQFIBAABCAAyFiEE8TM4V0tmI4mGbHaCv/vSX3jHroMFAlnSP50UHHBib256aW5p QHJlZGhhdC5jb20ACgkQv/vSX3jHroPJrAf/YDQtbpVvJMHbLATxPLJFDhHMS9Xu krmu0a5DA3u4H261iW9tI7gcuejOUDuZtiY0pRp/JVgErIjWFl00zhv0gYz/Ca62 JxGoJtvknmNBJhomLM7ZWp9JTI0aMuUrYuObdv7orTxPrsJl/lEbyLBxCHIkM6K5 yXZmLV2MOY+/A4OS3dFmSWq+MsH/TjSYtrvLfhKgjPd4mA+CQzcgXW0VCxGdppUf K4SE/cdz6OwPST4SqMfz/PnbhySkbvVsqawemhqI6w0GlrQ7y+HB2mJT/TRBtV0i 3I4hx/3HG/FO2pRMvrcf/80pDr6OXZyAZsXdXghDFo/4OixSl/JqM/GDTg== =RGTp -----END PGP SIGNATURE----- Merge remote-tracking branch 'remotes/bonzini/tags/for-upstream' into staging * iothread bugfix (Eduardo) * Linux headers sync (Dave) * .gitignore fix (Eric) * KVM capability check fixes (Greg) * kvmclock fix (Jim) # gpg: Signature made Mon 02 Oct 2017 14:31:09 BST # gpg: using RSA key 0xBFFBD25F78C7AE83 # gpg: Good signature from "Paolo Bonzini <bonzini@gnu.org>" # gpg: aka "Paolo Bonzini <pbonzini@redhat.com>" # Primary key fingerprint: 46F5 9FBD 57D6 12E7 BFD4 E2F7 7E15 100C CD36 69B1 # Subkey fingerprint: F133 3857 4B66 2389 866C 7682 BFFB D25F 78C7 AE83 * remotes/bonzini/tags/for-upstream: kvmclock: use the updated system_timer_msr kvm: check KVM_CAP_NR_VCPUS with kvm_vm_check_extension() kvm: check KVM_CAP_SYNC_MMU with kvm_vm_check_extension() linux-headers: sync against v4.14-rc1 iothread: Make iothread_stop() idempotent scsi: Ignore executable for in-tree builds Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Peter Maydell
commit
d147f7e815
|
|
@ -49,6 +49,7 @@
|
|||
/qemu-version.h
|
||||
/qemu-version.h.tmp
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||||
/module_block.h
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||||
/scsi/qemu-pr-helper
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||||
/vscclient
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||||
/vhost-user-scsi
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||||
/fsdev/virtfs-proxy-helper
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||||
|
|
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|||
|
|
@ -87,6 +87,7 @@ struct KVMState
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#endif
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||||
int many_ioeventfds;
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||||
int intx_set_mask;
|
||||
bool sync_mmu;
|
||||
/* The man page (and posix) say ioctl numbers are signed int, but
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* they're not. Linux, glibc and *BSD all treat ioctl numbers as
|
||||
* unsigned, and treating them as signed here can break things */
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|
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@ -1439,7 +1440,7 @@ static void kvm_irqchip_create(MachineState *machine, KVMState *s)
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*/
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static int kvm_recommended_vcpus(KVMState *s)
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{
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int ret = kvm_check_extension(s, KVM_CAP_NR_VCPUS);
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int ret = kvm_vm_check_extension(s, KVM_CAP_NR_VCPUS);
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return (ret) ? ret : 4;
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}
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@ -1529,26 +1530,6 @@ static int kvm_init(MachineState *ms)
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s->nr_slots = 32;
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}
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/* check the vcpu limits */
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soft_vcpus_limit = kvm_recommended_vcpus(s);
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hard_vcpus_limit = kvm_max_vcpus(s);
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while (nc->name) {
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if (nc->num > soft_vcpus_limit) {
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warn_report("Number of %s cpus requested (%d) exceeds "
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"the recommended cpus supported by KVM (%d)",
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nc->name, nc->num, soft_vcpus_limit);
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if (nc->num > hard_vcpus_limit) {
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fprintf(stderr, "Number of %s cpus requested (%d) exceeds "
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"the maximum cpus supported by KVM (%d)\n",
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nc->name, nc->num, hard_vcpus_limit);
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exit(1);
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}
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}
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nc++;
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}
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kvm_type = qemu_opt_get(qemu_get_machine_opts(), "kvm-type");
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if (mc->kvm_type) {
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type = mc->kvm_type(kvm_type);
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|
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@ -1583,6 +1564,27 @@ static int kvm_init(MachineState *ms)
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}
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s->vmfd = ret;
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/* check the vcpu limits */
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soft_vcpus_limit = kvm_recommended_vcpus(s);
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hard_vcpus_limit = kvm_max_vcpus(s);
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while (nc->name) {
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if (nc->num > soft_vcpus_limit) {
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warn_report("Number of %s cpus requested (%d) exceeds "
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"the recommended cpus supported by KVM (%d)",
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nc->name, nc->num, soft_vcpus_limit);
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if (nc->num > hard_vcpus_limit) {
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fprintf(stderr, "Number of %s cpus requested (%d) exceeds "
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"the maximum cpus supported by KVM (%d)\n",
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nc->name, nc->num, hard_vcpus_limit);
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exit(1);
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}
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}
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nc++;
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}
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missing_cap = kvm_check_extension_list(s, kvm_required_capabilites);
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if (!missing_cap) {
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missing_cap =
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|
|
@ -1664,6 +1666,8 @@ static int kvm_init(MachineState *ms)
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|
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s->many_ioeventfds = kvm_check_many_ioeventfds();
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|
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s->sync_mmu = !!kvm_vm_check_extension(kvm_state, KVM_CAP_SYNC_MMU);
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return 0;
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err:
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|
|
@ -2130,10 +2134,9 @@ int kvm_device_access(int fd, int group, uint64_t attr,
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return err;
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}
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/* Return 1 on success, 0 on failure */
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int kvm_has_sync_mmu(void)
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bool kvm_has_sync_mmu(void)
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{
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return kvm_check_extension(kvm_state, KVM_CAP_SYNC_MMU);
|
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return kvm_state->sync_mmu;
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}
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|
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int kvm_has_vcpu_events(void)
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|
|
|
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|
|
@ -64,9 +64,9 @@ int kvm_cpu_exec(CPUState *cpu)
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abort();
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}
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int kvm_has_sync_mmu(void)
|
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bool kvm_has_sync_mmu(void)
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{
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return 0;
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return false;
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}
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int kvm_has_many_ioeventfds(void)
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|
|
|
|||
|
|
@ -62,7 +62,7 @@ static uint64_t kvmclock_current_nsec(KVMClockState *s)
|
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{
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CPUState *cpu = first_cpu;
|
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CPUX86State *env = cpu->env_ptr;
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hwaddr kvmclock_struct_pa = env->system_time_msr & ~1ULL;
|
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hwaddr kvmclock_struct_pa;
|
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uint64_t migration_tsc = env->tsc;
|
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struct pvclock_vcpu_time_info time;
|
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uint64_t delta;
|
||||
|
|
@ -77,6 +77,7 @@ static uint64_t kvmclock_current_nsec(KVMClockState *s)
|
|||
return 0;
|
||||
}
|
||||
|
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kvmclock_struct_pa = env->system_time_msr & ~1ULL;
|
||||
cpu_physical_memory_read(kvmclock_struct_pa, &time, sizeof(time));
|
||||
|
||||
assert(time.tsc_timestamp <= migration_tsc);
|
||||
|
|
|
|||
|
|
@ -149,12 +149,9 @@
|
|||
*/
|
||||
#define HV_X64_DEPRECATING_AEOI_RECOMMENDED (1 << 9)
|
||||
|
||||
/*
|
||||
* HV_VP_SET available
|
||||
*/
|
||||
/* Recommend using the newer ExProcessorMasks interface */
|
||||
#define HV_X64_EX_PROCESSOR_MASKS_RECOMMENDED (1 << 11)
|
||||
|
||||
|
||||
/*
|
||||
* Crash notification flag.
|
||||
*/
|
||||
|
|
@ -242,7 +239,11 @@
|
|||
(~((1ull << HV_X64_MSR_HYPERCALL_PAGE_ADDRESS_SHIFT) - 1))
|
||||
|
||||
/* Declare the various hypercall operations. */
|
||||
#define HVCALL_FLUSH_VIRTUAL_ADDRESS_SPACE 0x0002
|
||||
#define HVCALL_FLUSH_VIRTUAL_ADDRESS_LIST 0x0003
|
||||
#define HVCALL_NOTIFY_LONG_SPIN_WAIT 0x0008
|
||||
#define HVCALL_FLUSH_VIRTUAL_ADDRESS_SPACE_EX 0x0013
|
||||
#define HVCALL_FLUSH_VIRTUAL_ADDRESS_LIST_EX 0x0014
|
||||
#define HVCALL_POST_MESSAGE 0x005c
|
||||
#define HVCALL_SIGNAL_EVENT 0x005d
|
||||
|
||||
|
|
@ -259,6 +260,16 @@
|
|||
#define HV_PROCESSOR_POWER_STATE_C2 2
|
||||
#define HV_PROCESSOR_POWER_STATE_C3 3
|
||||
|
||||
#define HV_FLUSH_ALL_PROCESSORS BIT(0)
|
||||
#define HV_FLUSH_ALL_VIRTUAL_ADDRESS_SPACES BIT(1)
|
||||
#define HV_FLUSH_NON_GLOBAL_MAPPINGS_ONLY BIT(2)
|
||||
#define HV_FLUSH_USE_EXTENDED_RANGE_FORMAT BIT(3)
|
||||
|
||||
enum HV_GENERIC_SET_FORMAT {
|
||||
HV_GENERIC_SET_SPARCE_4K,
|
||||
HV_GENERIC_SET_ALL,
|
||||
};
|
||||
|
||||
/* hypercall status code */
|
||||
#define HV_STATUS_SUCCESS 0
|
||||
#define HV_STATUS_INVALID_HYPERCALL_CODE 2
|
||||
|
|
|
|||
|
|
@ -513,6 +513,7 @@
|
|||
#define PCI_EXP_DEVSTA_URD 0x0008 /* Unsupported Request Detected */
|
||||
#define PCI_EXP_DEVSTA_AUXPD 0x0010 /* AUX Power Detected */
|
||||
#define PCI_EXP_DEVSTA_TRPND 0x0020 /* Transactions Pending */
|
||||
#define PCI_CAP_EXP_RC_ENDPOINT_SIZEOF_V1 12 /* v1 endpoints without link end here */
|
||||
#define PCI_EXP_LNKCAP 12 /* Link Capabilities */
|
||||
#define PCI_EXP_LNKCAP_SLS 0x0000000f /* Supported Link Speeds */
|
||||
#define PCI_EXP_LNKCAP_SLS_2_5GB 0x00000001 /* LNKCAP2 SLS Vector bit 0 */
|
||||
|
|
@ -556,7 +557,7 @@
|
|||
#define PCI_EXP_LNKSTA_DLLLA 0x2000 /* Data Link Layer Link Active */
|
||||
#define PCI_EXP_LNKSTA_LBMS 0x4000 /* Link Bandwidth Management Status */
|
||||
#define PCI_EXP_LNKSTA_LABS 0x8000 /* Link Autonomous Bandwidth Status */
|
||||
#define PCI_CAP_EXP_ENDPOINT_SIZEOF_V1 20 /* v1 endpoints end here */
|
||||
#define PCI_CAP_EXP_ENDPOINT_SIZEOF_V1 20 /* v1 endpoints with link end here */
|
||||
#define PCI_EXP_SLTCAP 20 /* Slot Capabilities */
|
||||
#define PCI_EXP_SLTCAP_ABP 0x00000001 /* Attention Button Present */
|
||||
#define PCI_EXP_SLTCAP_PCP 0x00000002 /* Power Controller Present */
|
||||
|
|
@ -639,7 +640,7 @@
|
|||
#define PCI_EXP_DEVCTL2_OBFF_MSGB_EN 0x4000 /* Enable OBFF Message type B */
|
||||
#define PCI_EXP_DEVCTL2_OBFF_WAKE_EN 0x6000 /* OBFF using WAKE# signaling */
|
||||
#define PCI_EXP_DEVSTA2 42 /* Device Status 2 */
|
||||
#define PCI_CAP_EXP_ENDPOINT_SIZEOF_V2 44 /* v2 endpoints end here */
|
||||
#define PCI_CAP_EXP_RC_ENDPOINT_SIZEOF_V2 44 /* v2 endpoints without link end here */
|
||||
#define PCI_EXP_LNKCAP2 44 /* Link Capabilities 2 */
|
||||
#define PCI_EXP_LNKCAP2_SLS_2_5GB 0x00000002 /* Supported Speed 2.5GT/s */
|
||||
#define PCI_EXP_LNKCAP2_SLS_5_0GB 0x00000004 /* Supported Speed 5.0GT/s */
|
||||
|
|
@ -647,6 +648,7 @@
|
|||
#define PCI_EXP_LNKCAP2_CROSSLINK 0x00000100 /* Crosslink supported */
|
||||
#define PCI_EXP_LNKCTL2 48 /* Link Control 2 */
|
||||
#define PCI_EXP_LNKSTA2 50 /* Link Status 2 */
|
||||
#define PCI_CAP_EXP_ENDPOINT_SIZEOF_V2 52 /* v2 endpoints with link end here */
|
||||
#define PCI_EXP_SLTCAP2 52 /* Slot Capabilities 2 */
|
||||
#define PCI_EXP_SLTCTL2 56 /* Slot Control 2 */
|
||||
#define PCI_EXP_SLTSTA2 58 /* Slot Status 2 */
|
||||
|
|
@ -733,23 +735,17 @@
|
|||
#define PCI_ERR_CAP_ECRC_CHKE 0x00000100 /* ECRC Check Enable */
|
||||
#define PCI_ERR_HEADER_LOG 28 /* Header Log Register (16 bytes) */
|
||||
#define PCI_ERR_ROOT_COMMAND 44 /* Root Error Command */
|
||||
/* Correctable Err Reporting Enable */
|
||||
#define PCI_ERR_ROOT_CMD_COR_EN 0x00000001
|
||||
/* Non-fatal Err Reporting Enable */
|
||||
#define PCI_ERR_ROOT_CMD_NONFATAL_EN 0x00000002
|
||||
/* Fatal Err Reporting Enable */
|
||||
#define PCI_ERR_ROOT_CMD_FATAL_EN 0x00000004
|
||||
#define PCI_ERR_ROOT_CMD_COR_EN 0x00000001 /* Correctable Err Reporting Enable */
|
||||
#define PCI_ERR_ROOT_CMD_NONFATAL_EN 0x00000002 /* Non-Fatal Err Reporting Enable */
|
||||
#define PCI_ERR_ROOT_CMD_FATAL_EN 0x00000004 /* Fatal Err Reporting Enable */
|
||||
#define PCI_ERR_ROOT_STATUS 48
|
||||
#define PCI_ERR_ROOT_COR_RCV 0x00000001 /* ERR_COR Received */
|
||||
/* Multi ERR_COR Received */
|
||||
#define PCI_ERR_ROOT_MULTI_COR_RCV 0x00000002
|
||||
/* ERR_FATAL/NONFATAL Received */
|
||||
#define PCI_ERR_ROOT_UNCOR_RCV 0x00000004
|
||||
/* Multi ERR_FATAL/NONFATAL Received */
|
||||
#define PCI_ERR_ROOT_MULTI_UNCOR_RCV 0x00000008
|
||||
#define PCI_ERR_ROOT_FIRST_FATAL 0x00000010 /* First Fatal */
|
||||
#define PCI_ERR_ROOT_NONFATAL_RCV 0x00000020 /* Non-Fatal Received */
|
||||
#define PCI_ERR_ROOT_FATAL_RCV 0x00000040 /* Fatal Received */
|
||||
#define PCI_ERR_ROOT_COR_RCV 0x00000001 /* ERR_COR Received */
|
||||
#define PCI_ERR_ROOT_MULTI_COR_RCV 0x00000002 /* Multiple ERR_COR */
|
||||
#define PCI_ERR_ROOT_UNCOR_RCV 0x00000004 /* ERR_FATAL/NONFATAL */
|
||||
#define PCI_ERR_ROOT_MULTI_UNCOR_RCV 0x00000008 /* Multiple FATAL/NONFATAL */
|
||||
#define PCI_ERR_ROOT_FIRST_FATAL 0x00000010 /* First UNC is Fatal */
|
||||
#define PCI_ERR_ROOT_NONFATAL_RCV 0x00000020 /* Non-Fatal Received */
|
||||
#define PCI_ERR_ROOT_FATAL_RCV 0x00000040 /* Fatal Received */
|
||||
#define PCI_ERR_ROOT_ERR_SRC 52 /* Error Source Identification */
|
||||
|
||||
/* Virtual Channel */
|
||||
|
|
@ -967,6 +963,7 @@
|
|||
#define PCI_EXP_DPC_CAP_RP_EXT 0x20 /* Root Port Extensions for DPC */
|
||||
#define PCI_EXP_DPC_CAP_POISONED_TLP 0x40 /* Poisoned TLP Egress Blocking Supported */
|
||||
#define PCI_EXP_DPC_CAP_SW_TRIGGER 0x80 /* Software Triggering Supported */
|
||||
#define PCI_EXP_DPC_RP_PIO_LOG_SIZE 0xF00 /* RP PIO log size */
|
||||
#define PCI_EXP_DPC_CAP_DL_ACTIVE 0x1000 /* ERR_COR signal on DL_Active supported */
|
||||
|
||||
#define PCI_EXP_DPC_CTL 6 /* DPC control */
|
||||
|
|
@ -980,6 +977,15 @@
|
|||
|
||||
#define PCI_EXP_DPC_SOURCE_ID 10 /* DPC Source Identifier */
|
||||
|
||||
#define PCI_EXP_DPC_RP_PIO_STATUS 0x0C /* RP PIO Status */
|
||||
#define PCI_EXP_DPC_RP_PIO_MASK 0x10 /* RP PIO MASK */
|
||||
#define PCI_EXP_DPC_RP_PIO_SEVERITY 0x14 /* RP PIO Severity */
|
||||
#define PCI_EXP_DPC_RP_PIO_SYSERROR 0x18 /* RP PIO SysError */
|
||||
#define PCI_EXP_DPC_RP_PIO_EXCEPTION 0x1C /* RP PIO Exception */
|
||||
#define PCI_EXP_DPC_RP_PIO_HEADER_LOG 0x20 /* RP PIO Header Log */
|
||||
#define PCI_EXP_DPC_RP_PIO_IMPSPEC_LOG 0x30 /* RP PIO ImpSpec Log */
|
||||
#define PCI_EXP_DPC_RP_PIO_TLPPREFIX_LOG 0x34 /* RP PIO TLP Prefix Log */
|
||||
|
||||
/* Precision Time Measurement */
|
||||
#define PCI_PTM_CAP 0x04 /* PTM Capability */
|
||||
#define PCI_PTM_CAP_REQ 0x00000001 /* Requester capable */
|
||||
|
|
|
|||
|
|
@ -1,7 +1,7 @@
|
|||
#ifndef _LINUX_VIRTIO_RING_H
|
||||
#define _LINUX_VIRTIO_RING_H
|
||||
/* An interface for efficient virtio implementation, currently for use by KVM
|
||||
* and lguest, but hopefully others soon. Do NOT change this since it will
|
||||
/* An interface for efficient virtio implementation, currently for use by KVM,
|
||||
* but hopefully others soon. Do NOT change this since it will
|
||||
* break existing servers and clients.
|
||||
*
|
||||
* This header is BSD licensed so anyone can use the definitions to implement
|
||||
|
|
|
|||
|
|
@ -207,7 +207,7 @@ extern KVMState *kvm_state;
|
|||
/* external API */
|
||||
|
||||
bool kvm_has_free_slot(MachineState *ms);
|
||||
int kvm_has_sync_mmu(void);
|
||||
bool kvm_has_sync_mmu(void);
|
||||
int kvm_has_vcpu_events(void);
|
||||
int kvm_has_robust_singlestep(void);
|
||||
int kvm_has_debugregs(void);
|
||||
|
|
|
|||
|
|
@ -85,7 +85,7 @@ static int iothread_stop(Object *object, void *opaque)
|
|||
IOThread *iothread;
|
||||
|
||||
iothread = (IOThread *)object_dynamic_cast(object, TYPE_IOTHREAD);
|
||||
if (!iothread || !iothread->ctx) {
|
||||
if (!iothread || !iothread->ctx || iothread->stopping) {
|
||||
return 0;
|
||||
}
|
||||
iothread->stopping = true;
|
||||
|
|
|
|||
|
|
@ -88,6 +88,12 @@ struct kvm_s390_io_adapter_req {
|
|||
/* kvm attributes for KVM_S390_VM_TOD */
|
||||
#define KVM_S390_VM_TOD_LOW 0
|
||||
#define KVM_S390_VM_TOD_HIGH 1
|
||||
#define KVM_S390_VM_TOD_EXT 2
|
||||
|
||||
struct kvm_s390_vm_tod_clock {
|
||||
__u8 epoch_idx;
|
||||
__u64 tod;
|
||||
};
|
||||
|
||||
/* kvm attributes for KVM_S390_VM_CPU_MODEL */
|
||||
/* processor related attributes are r/w */
|
||||
|
|
|
|||
|
|
@ -711,7 +711,8 @@ struct kvm_ppc_one_seg_page_size {
|
|||
struct kvm_ppc_smmu_info {
|
||||
__u64 flags;
|
||||
__u32 slb_size;
|
||||
__u32 pad;
|
||||
__u16 data_keys; /* # storage keys supported for data */
|
||||
__u16 instr_keys; /* # storage keys supported for instructions */
|
||||
struct kvm_ppc_one_seg_page_size sps[KVM_PPC_PAGE_SIZES_MAX_SZ];
|
||||
};
|
||||
|
||||
|
|
|
|||
|
|
@ -23,7 +23,9 @@
|
|||
UFFD_FEATURE_EVENT_REMOVE | \
|
||||
UFFD_FEATURE_EVENT_UNMAP | \
|
||||
UFFD_FEATURE_MISSING_HUGETLBFS | \
|
||||
UFFD_FEATURE_MISSING_SHMEM)
|
||||
UFFD_FEATURE_MISSING_SHMEM | \
|
||||
UFFD_FEATURE_SIGBUS | \
|
||||
UFFD_FEATURE_THREAD_ID)
|
||||
#define UFFD_API_IOCTLS \
|
||||
((__u64)1 << _UFFDIO_REGISTER | \
|
||||
(__u64)1 << _UFFDIO_UNREGISTER | \
|
||||
|
|
@ -78,6 +80,9 @@ struct uffd_msg {
|
|||
struct {
|
||||
__u64 flags;
|
||||
__u64 address;
|
||||
union {
|
||||
__u32 ptid;
|
||||
} feat;
|
||||
} pagefault;
|
||||
|
||||
struct {
|
||||
|
|
@ -153,6 +158,13 @@ struct uffdio_api {
|
|||
* UFFD_FEATURE_MISSING_SHMEM works the same as
|
||||
* UFFD_FEATURE_MISSING_HUGETLBFS, but it applies to shmem
|
||||
* (i.e. tmpfs and other shmem based APIs).
|
||||
*
|
||||
* UFFD_FEATURE_SIGBUS feature means no page-fault
|
||||
* (UFFD_EVENT_PAGEFAULT) event will be delivered, instead
|
||||
* a SIGBUS signal will be sent to the faulting process.
|
||||
*
|
||||
* UFFD_FEATURE_THREAD_ID pid of the page faulted task_struct will
|
||||
* be returned, if feature is not requested 0 will be returned.
|
||||
*/
|
||||
#define UFFD_FEATURE_PAGEFAULT_FLAG_WP (1<<0)
|
||||
#define UFFD_FEATURE_EVENT_FORK (1<<1)
|
||||
|
|
@ -161,6 +173,8 @@ struct uffdio_api {
|
|||
#define UFFD_FEATURE_MISSING_HUGETLBFS (1<<4)
|
||||
#define UFFD_FEATURE_MISSING_SHMEM (1<<5)
|
||||
#define UFFD_FEATURE_EVENT_UNMAP (1<<6)
|
||||
#define UFFD_FEATURE_SIGBUS (1<<7)
|
||||
#define UFFD_FEATURE_THREAD_ID (1<<8)
|
||||
__u64 features;
|
||||
|
||||
__u64 ioctls;
|
||||
|
|
|
|||
Loading…
Reference in New Issue