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target-ppc: Add POWER8's TIR SPR

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This adds TIR (Thread Identification Register) SPR first defined for server
CPUs in PowerISA 2.07.

Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru>
Reviewed-by: Tom Musta <tommusta@gmail.com>
Signed-off-by: Alexander Graf <agraf@suse.de>
This commit is contained in:
Alexey Kardashevskiy 2014-06-04 22:50:55 +10:00 committed by Alexander Graf
parent a242881405
commit d1a721ab81
2 changed files with 11 additions and 0 deletions
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1
target-ppc/cpu.h
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@ -1370,6 +1370,7 @@ static inline int cpu_mmu_index (CPUPPCState *env)
#define SPR_BOOKE_GIVOR8 (0x1BB)
#define SPR_BOOKE_GIVOR13 (0x1BC)
#define SPR_BOOKE_GIVOR14 (0x1BD)
#define SPR_TIR (0x1BE)
#define SPR_BOOKE_SPEFSCR (0x200)
#define SPR_Exxx_BBEAR (0x201)
#define SPR_Exxx_BBTAR (0x202)

10
target-ppc/translate_init.c
View File

@ -7518,6 +7518,15 @@ static void gen_spr_book3s_ids(CPUPPCState *env)
0x00000000);
}
static void gen_spr_power8_ids(CPUPPCState *env)
{
/* Thread identification */
spr_register(env, SPR_TIR, "TIR",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, SPR_NOACCESS,
0x00000000);
}
static void gen_spr_book3s_purr(CPUPPCState *env)
{
#if !defined(CONFIG_USER_ONLY)
@ -7621,6 +7630,7 @@ static void init_proc_book3s_64(CPUPPCState *env, int version)
}
if (version >= BOOK3S_CPU_POWER8) {
gen_spr_power8_tce_address_control(env);
gen_spr_power8_ids(env);
}
#if !defined(CONFIG_USER_ONLY)
switch (version) {