target/mips/mxu: Add S32/D16/Q8- MOVZ/MOVN instructions
These instructions are: - single 32-bit - dual 16-bit packed - quad 8-bit packed conditional moves. They are grouped in pool20 in the source code. Signed-off-by: Siarhei Volkau <lis8215@gmail.com> Message-Id: <20230608104222.1520143-29-lis8215@gmail.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
This commit is contained in:
Siarhei Volkau
Philippe Mathieu-Daudé
parent
07c92895d7
commit
d1b6ded4f7
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@ -403,6 +403,7 @@ enum {
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OPC_MXU__POOL18 = 0x36,
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OPC_MXU_Q16SAR = 0x37,
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OPC_MXU__POOL19 = 0x38,
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OPC_MXU__POOL20 = 0x39,
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};
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@ -541,6 +542,18 @@ enum {
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OPC_MXU_Q8MULSU = 0x01,
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};
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/*
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* MXU pool 20
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*/
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enum {
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OPC_MXU_Q8MOVZ = 0x00,
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OPC_MXU_Q8MOVN = 0x01,
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OPC_MXU_D16MOVZ = 0x02,
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OPC_MXU_D16MOVN = 0x03,
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OPC_MXU_S32MOVZ = 0x04,
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OPC_MXU_S32MOVN = 0x05,
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};
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/* MXU accumulate add/subtract 1-bit pattern 'aptn1' */
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#define MXU_APTN1_A 0
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#define MXU_APTN1_S 1
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@ -1993,6 +2006,8 @@ static void gen_mxu_q16sxxv(DisasContext *ctx, bool right, bool arithmetic)
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* Q8SLTU
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* D16AVG Q8AVG
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* D16AVGR Q8AVGR
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* S32MOVZ D16MOVZ Q8MOVZ
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* S32MOVN D16MOVN Q8MOVN
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*/
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/*
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@ -2491,6 +2506,146 @@ static void gen_mxu_q8avg(DisasContext *ctx, bool round45)
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}
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}
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/*
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* Q8MOVZ
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* Quadruple 8-bit packed conditional move where
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* XRb contains conditions, XRc what to move and
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* XRa is the destination.
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* a.k.a. if (XRb[0..3] == 0) { XRa[0..3] = XRc[0..3] }
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*
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* Q8MOVN
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* Quadruple 8-bit packed conditional move where
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* XRb contains conditions, XRc what to move and
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* XRa is the destination.
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* a.k.a. if (XRb[0..3] != 0) { XRa[0..3] = XRc[0..3] }
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*/
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static void gen_mxu_q8movzn(DisasContext *ctx, TCGCond cond)
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{
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uint32_t XRc, XRb, XRa;
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XRa = extract32(ctx->opcode, 6, 4);
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XRb = extract32(ctx->opcode, 10, 4);
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XRc = extract32(ctx->opcode, 14, 4);
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TCGv t0 = tcg_temp_new();
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TCGv t1 = tcg_temp_new();
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TCGv t2 = tcg_temp_new();
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TCGv t3 = tcg_temp_new();
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TCGLabel *l_quarterdone = gen_new_label();
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TCGLabel *l_halfdone = gen_new_label();
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TCGLabel *l_quarterrest = gen_new_label();
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TCGLabel *l_done = gen_new_label();
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gen_load_mxu_gpr(t0, XRc);
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gen_load_mxu_gpr(t1, XRb);
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gen_load_mxu_gpr(t2, XRa);
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tcg_gen_extract_tl(t3, t1, 24, 8);
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tcg_gen_brcondi_tl(cond, t3, 0, l_quarterdone);
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tcg_gen_extract_tl(t3, t0, 24, 8);
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tcg_gen_deposit_tl(t2, t2, t3, 24, 8);
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gen_set_label(l_quarterdone);
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tcg_gen_extract_tl(t3, t1, 16, 8);
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tcg_gen_brcondi_tl(cond, t3, 0, l_halfdone);
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tcg_gen_extract_tl(t3, t0, 16, 8);
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tcg_gen_deposit_tl(t2, t2, t3, 16, 8);
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gen_set_label(l_halfdone);
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tcg_gen_extract_tl(t3, t1, 8, 8);
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tcg_gen_brcondi_tl(cond, t3, 0, l_quarterrest);
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tcg_gen_extract_tl(t3, t0, 8, 8);
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tcg_gen_deposit_tl(t2, t2, t3, 8, 8);
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gen_set_label(l_quarterrest);
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tcg_gen_extract_tl(t3, t1, 0, 8);
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tcg_gen_brcondi_tl(cond, t3, 0, l_done);
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tcg_gen_extract_tl(t3, t0, 0, 8);
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tcg_gen_deposit_tl(t2, t2, t3, 0, 8);
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gen_set_label(l_done);
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gen_store_mxu_gpr(t2, XRa);
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}
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/*
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* D16MOVZ
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* Double 16-bit packed conditional move where
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* XRb contains conditions, XRc what to move and
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* XRa is the destination.
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* a.k.a. if (XRb[0..1] == 0) { XRa[0..1] = XRc[0..1] }
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*
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* D16MOVN
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* Double 16-bit packed conditional move where
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* XRb contains conditions, XRc what to move and
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* XRa is the destination.
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* a.k.a. if (XRb[0..3] != 0) { XRa[0..1] = XRc[0..1] }
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*/
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static void gen_mxu_d16movzn(DisasContext *ctx, TCGCond cond)
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{
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uint32_t XRc, XRb, XRa;
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XRa = extract32(ctx->opcode, 6, 4);
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XRb = extract32(ctx->opcode, 10, 4);
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XRc = extract32(ctx->opcode, 14, 4);
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TCGv t0 = tcg_temp_new();
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TCGv t1 = tcg_temp_new();
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TCGv t2 = tcg_temp_new();
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TCGv t3 = tcg_temp_new();
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TCGLabel *l_halfdone = gen_new_label();
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TCGLabel *l_done = gen_new_label();
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gen_load_mxu_gpr(t0, XRc);
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gen_load_mxu_gpr(t1, XRb);
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gen_load_mxu_gpr(t2, XRa);
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tcg_gen_extract_tl(t3, t1, 16, 16);
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tcg_gen_brcondi_tl(cond, t3, 0, l_halfdone);
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tcg_gen_extract_tl(t3, t0, 16, 16);
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tcg_gen_deposit_tl(t2, t2, t3, 16, 16);
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gen_set_label(l_halfdone);
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tcg_gen_extract_tl(t3, t1, 0, 16);
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tcg_gen_brcondi_tl(cond, t3, 0, l_done);
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tcg_gen_extract_tl(t3, t0, 0, 16);
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tcg_gen_deposit_tl(t2, t2, t3, 0, 16);
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gen_set_label(l_done);
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gen_store_mxu_gpr(t2, XRa);
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}
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/*
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* S32MOVZ
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* Quadruple 32-bit conditional move where
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* XRb contains conditions, XRc what to move and
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* XRa is the destination.
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* a.k.a. if (XRb == 0) { XRa = XRc }
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*
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* S32MOVN
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* Single 32-bit conditional move where
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* XRb contains conditions, XRc what to move and
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* XRa is the destination.
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* a.k.a. if (XRb != 0) { XRa = XRc }
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*/
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static void gen_mxu_s32movzn(DisasContext *ctx, TCGCond cond)
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{
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uint32_t XRc, XRb, XRa;
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XRa = extract32(ctx->opcode, 6, 4);
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XRb = extract32(ctx->opcode, 10, 4);
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XRc = extract32(ctx->opcode, 14, 4);
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TCGv t0 = tcg_temp_new();
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TCGv t1 = tcg_temp_new();
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TCGLabel *l_done = gen_new_label();
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gen_load_mxu_gpr(t0, XRc);
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gen_load_mxu_gpr(t1, XRb);
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tcg_gen_brcondi_tl(cond, t1, 0, l_done);
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gen_store_mxu_gpr(t0, XRa);
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gen_set_label(l_done);
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}
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/*
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* MXU instruction category: Addition and subtraction
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@ -4407,6 +4562,36 @@ static void decode_opc_mxu__pool19(DisasContext *ctx)
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}
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}
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static void decode_opc_mxu__pool20(DisasContext *ctx)
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{
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uint32_t opcode = extract32(ctx->opcode, 18, 3);
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switch (opcode) {
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case OPC_MXU_Q8MOVZ:
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gen_mxu_q8movzn(ctx, TCG_COND_NE);
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break;
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case OPC_MXU_Q8MOVN:
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gen_mxu_q8movzn(ctx, TCG_COND_EQ);
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break;
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case OPC_MXU_D16MOVZ:
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gen_mxu_d16movzn(ctx, TCG_COND_NE);
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break;
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case OPC_MXU_D16MOVN:
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gen_mxu_d16movzn(ctx, TCG_COND_EQ);
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break;
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case OPC_MXU_S32MOVZ:
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gen_mxu_s32movzn(ctx, TCG_COND_NE);
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break;
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case OPC_MXU_S32MOVN:
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gen_mxu_s32movzn(ctx, TCG_COND_EQ);
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break;
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default:
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MIPS_INVAL("decode_opc_mxu");
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gen_reserved_instruction(ctx);
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break;
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}
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}
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bool decode_ase_mxu(DisasContext *ctx, uint32_t insn)
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{
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uint32_t opcode = extract32(insn, 0, 6);
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@ -4567,6 +4752,9 @@ bool decode_ase_mxu(DisasContext *ctx, uint32_t insn)
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case OPC_MXU__POOL19:
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decode_opc_mxu__pool19(ctx);
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break;
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case OPC_MXU__POOL20:
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decode_opc_mxu__pool20(ctx);
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break;
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default:
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return false;
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}
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