target/riscv: Implement AIA xiselect and xireg CSRs
The AIA specification defines [m|s|vs]iselect and [m|s|vs]ireg CSRs which allow indirect access to interrupt priority arrays and per-HART IMSIC registers. This patch implements AIA xiselect and xireg CSRs. Signed-off-by: Anup Patel <anup.patel@wdc.com> Signed-off-by: Anup Patel <anup@brainfault.org> Reviewed-by: Frank Chang <frank.chang@sifive.com> Message-id: 20220204174700.534953-15-anup@brainfault.org Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
This commit is contained in:
Anup Patel
Alistair Francis
parent
c7de92b4e8
commit
d1ceff405a
@ -196,6 +196,10 @@ struct CPURISCVState {
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uint8_t miprio[64];
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uint8_t siprio[64];
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/* AIA CSRs */
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target_ulong miselect;
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target_ulong siselect;
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/* Hypervisor CSRs */
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target_ulong hstatus;
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target_ulong hedeleg;
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@ -229,6 +233,9 @@ struct CPURISCVState {
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target_ulong vstval;
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target_ulong vsatp;
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/* AIA VS-mode CSRs */
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target_ulong vsiselect;
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target_ulong mtval2;
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target_ulong mtinst;
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@ -931,6 +931,169 @@ static int read_mtopi(CPURISCVState *env, int csrno, target_ulong *val)
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return RISCV_EXCP_NONE;
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}
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static int aia_xlate_vs_csrno(CPURISCVState *env, int csrno)
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{
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if (!riscv_cpu_virt_enabled(env)) {
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return csrno;
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}
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switch (csrno) {
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case CSR_SISELECT:
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return CSR_VSISELECT;
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case CSR_SIREG:
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return CSR_VSIREG;
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default:
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return csrno;
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};
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}
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static int rmw_xiselect(CPURISCVState *env, int csrno, target_ulong *val,
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target_ulong new_val, target_ulong wr_mask)
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{
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target_ulong *iselect;
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/* Translate CSR number for VS-mode */
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csrno = aia_xlate_vs_csrno(env, csrno);
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/* Find the iselect CSR based on CSR number */
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switch (csrno) {
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case CSR_MISELECT:
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iselect = &env->miselect;
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break;
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case CSR_SISELECT:
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iselect = &env->siselect;
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break;
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case CSR_VSISELECT:
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iselect = &env->vsiselect;
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break;
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default:
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return RISCV_EXCP_ILLEGAL_INST;
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};
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if (val) {
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*val = *iselect;
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}
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wr_mask &= ISELECT_MASK;
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if (wr_mask) {
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*iselect = (*iselect & ~wr_mask) | (new_val & wr_mask);
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}
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return RISCV_EXCP_NONE;
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}
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static int rmw_iprio(target_ulong xlen,
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target_ulong iselect, uint8_t *iprio,
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target_ulong *val, target_ulong new_val,
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target_ulong wr_mask, int ext_irq_no)
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{
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int i, firq, nirqs;
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target_ulong old_val;
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if (iselect < ISELECT_IPRIO0 || ISELECT_IPRIO15 < iselect) {
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return -EINVAL;
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}
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if (xlen != 32 && iselect & 0x1) {
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return -EINVAL;
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}
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nirqs = 4 * (xlen / 32);
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firq = ((iselect - ISELECT_IPRIO0) / (xlen / 32)) * (nirqs);
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old_val = 0;
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for (i = 0; i < nirqs; i++) {
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old_val |= ((target_ulong)iprio[firq + i]) << (IPRIO_IRQ_BITS * i);
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}
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if (val) {
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*val = old_val;
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}
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if (wr_mask) {
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new_val = (old_val & ~wr_mask) | (new_val & wr_mask);
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for (i = 0; i < nirqs; i++) {
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/*
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* M-level and S-level external IRQ priority always read-only
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* zero. This means default priority order is always preferred
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* for M-level and S-level external IRQs.
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*/
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if ((firq + i) == ext_irq_no) {
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continue;
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}
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iprio[firq + i] = (new_val >> (IPRIO_IRQ_BITS * i)) & 0xff;
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}
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}
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return 0;
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}
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static int rmw_xireg(CPURISCVState *env, int csrno, target_ulong *val,
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target_ulong new_val, target_ulong wr_mask)
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{
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bool virt;
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uint8_t *iprio;
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int ret = -EINVAL;
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target_ulong priv, isel, vgein;
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/* Translate CSR number for VS-mode */
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csrno = aia_xlate_vs_csrno(env, csrno);
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/* Decode register details from CSR number */
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virt = false;
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switch (csrno) {
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case CSR_MIREG:
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iprio = env->miprio;
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isel = env->miselect;
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priv = PRV_M;
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break;
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case CSR_SIREG:
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iprio = env->siprio;
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isel = env->siselect;
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priv = PRV_S;
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break;
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case CSR_VSIREG:
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iprio = env->hviprio;
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isel = env->vsiselect;
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priv = PRV_S;
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virt = true;
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break;
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default:
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goto done;
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};
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/* Find the selected guest interrupt file */
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vgein = (virt) ? get_field(env->hstatus, HSTATUS_VGEIN) : 0;
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if (ISELECT_IPRIO0 <= isel && isel <= ISELECT_IPRIO15) {
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/* Local interrupt priority registers not available for VS-mode */
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if (!virt) {
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ret = rmw_iprio(riscv_cpu_mxl_bits(env),
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isel, iprio, val, new_val, wr_mask,
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(priv == PRV_M) ? IRQ_M_EXT : IRQ_S_EXT);
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}
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} else if (ISELECT_IMSIC_FIRST <= isel && isel <= ISELECT_IMSIC_LAST) {
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/* IMSIC registers only available when machine implements it. */
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if (env->aia_ireg_rmw_fn[priv]) {
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/* Selected guest interrupt file should not be zero */
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if (virt && (!vgein || env->geilen < vgein)) {
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goto done;
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}
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/* Call machine specific IMSIC register emulation */
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ret = env->aia_ireg_rmw_fn[priv](env->aia_ireg_rmw_fn_arg[priv],
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AIA_MAKE_IREG(isel, priv, virt, vgein,
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riscv_cpu_mxl_bits(env)),
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val, new_val, wr_mask);
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}
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}
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done:
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if (ret) {
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return (riscv_cpu_virt_enabled(env) && virt) ?
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RISCV_EXCP_VIRT_INSTRUCTION_FAULT : RISCV_EXCP_ILLEGAL_INST;
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}
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return RISCV_EXCP_NONE;
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}
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static RISCVException read_mtvec(CPURISCVState *env, int csrno,
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target_ulong *val)
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{
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@ -2760,6 +2923,10 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = {
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[CSR_MTVAL] = { "mtval", any, read_mtval, write_mtval },
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[CSR_MIP] = { "mip", any, NULL, NULL, rmw_mip },
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/* Machine-Level Window to Indirectly Accessed Registers (AIA) */
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[CSR_MISELECT] = { "miselect", aia_any, NULL, NULL, rmw_xiselect },
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[CSR_MIREG] = { "mireg", aia_any, NULL, NULL, rmw_xireg },
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/* Machine-Level Interrupts (AIA) */
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[CSR_MTOPI] = { "mtopi", aia_any, read_mtopi },
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@ -2792,6 +2959,10 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = {
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/* Supervisor Protection and Translation */
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[CSR_SATP] = { "satp", smode, read_satp, write_satp },
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/* Supervisor-Level Window to Indirectly Accessed Registers (AIA) */
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[CSR_SISELECT] = { "siselect", aia_smode, NULL, NULL, rmw_xiselect },
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[CSR_SIREG] = { "sireg", aia_smode, NULL, NULL, rmw_xireg },
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/* Supervisor-Level Interrupts (AIA) */
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[CSR_STOPI] = { "stopi", aia_smode, read_stopi },
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@ -2833,6 +3004,12 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = {
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[CSR_HVIPRIO1] = { "hviprio1", aia_hmode, read_hviprio1, write_hviprio1 },
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[CSR_HVIPRIO2] = { "hviprio2", aia_hmode, read_hviprio2, write_hviprio2 },
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/*
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* VS-Level Window to Indirectly Accessed Registers (H-extension with AIA)
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*/
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[CSR_VSISELECT] = { "vsiselect", aia_hmode, NULL, NULL, rmw_xiselect },
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[CSR_VSIREG] = { "vsireg", aia_hmode, NULL, NULL, rmw_xireg },
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/* VS-Level Interrupts (H-extension with AIA) */
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[CSR_VSTOPI] = { "vstopi", aia_hmode, read_vstopi },
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@ -103,6 +103,7 @@ static const VMStateDescription vmstate_hyper = {
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VMSTATE_UINTTL(env.vscause, RISCVCPU),
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VMSTATE_UINTTL(env.vstval, RISCVCPU),
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VMSTATE_UINTTL(env.vsatp, RISCVCPU),
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VMSTATE_UINTTL(env.vsiselect, RISCVCPU),
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VMSTATE_UINTTL(env.mtval2, RISCVCPU),
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VMSTATE_UINTTL(env.mtinst, RISCVCPU),
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@ -272,6 +273,8 @@ const VMStateDescription vmstate_riscv_cpu = {
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VMSTATE_UINTTL(env.mepc, RISCVCPU),
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VMSTATE_UINTTL(env.mcause, RISCVCPU),
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VMSTATE_UINTTL(env.mtval, RISCVCPU),
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VMSTATE_UINTTL(env.miselect, RISCVCPU),
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VMSTATE_UINTTL(env.siselect, RISCVCPU),
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VMSTATE_UINTTL(env.scounteren, RISCVCPU),
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VMSTATE_UINTTL(env.mcounteren, RISCVCPU),
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VMSTATE_UINTTL(env.sscratch, RISCVCPU),
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