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target/riscv/debug.c: keep experimental rv128 support working

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Add an MXL_RV128 case in two switches so that no error is triggered when
using the -cpu x-rv128 option.

Signed-off-by: Frédéric Pétrot <frederic.petrot@univ-grenoble-alpes.fr>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Message-Id: <20220602155246.38837-1-frederic.petrot@univ-grenoble-alpes.fr>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
This commit is contained in:
Frédéric Pétrot 2022-06-02 17:52:46 +02:00 committed by Alistair Francis
parent 8f42415fc1
commit d1d8541217
1 changed files with 2 additions and 0 deletions
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target/riscv/debug.c
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@ -77,6 +77,7 @@ static inline target_ulong trigger_type(CPURISCVState *env,
tdata1 = RV32_TYPE(type);
break;
case MXL_RV64:
case MXL_RV128:
tdata1 = RV64_TYPE(type);
break;
default:
@ -123,6 +124,7 @@ static target_ulong tdata1_validate(CPURISCVState *env, target_ulong val,
tdata1 = RV32_TYPE(t);
break;
case MXL_RV64:
case MXL_RV128:
type = extract64(val, 60, 4);
dmode = extract64(val, 59, 1);
tdata1 = RV64_TYPE(t);