OpenE2K/qemu-e2k
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target: e2k: Add %upsr.

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Denis Drakhnia 2020-11-23 22:48:58 +02:00 committed by Denis Drakhnia
parent 17835f1c1d
commit d1df754c9d
3 changed files with 33 additions and 1 deletions
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27
target/e2k/cpu.h
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@ -186,6 +186,31 @@ void e2k_tcg_initialize(void);
#define LSR_STRMD_LEN (LSR_STRMD_END - LSR_STRMD_OFF + 1)
#define LSR_SEMC_OFF /* side effects manual control */
#define UPSR_FE_OFF 0 /* floating point enable */
#define UPSR_FE_BIT 1
#define UPSR_SE_OFF 1 /* supervisor mode enable (only for Intel) */
#define UPSR_SE_BIT (1 << UPSR_SE_OFF)
#define UPSR_AC_OFF 2 /* not-aligned access control */
#define UPSR_AC_BIT (1 << UPSR_AC_OFF)
#define UPSR_DI_OFF 3 /* delayed interrupt (only for Intel) */
#define UPSR_DI_BIT (1 << UPSR_DI_OFF)
#define UPSR_WP_OFF 4 /* write protection (only for Intel) */
#define UPSR_WP_BIT (1 << UPSR_WP_OFF)
#define UPSR_IE_OFF 5 /* interrupt enable */
#define UPSR_IE_BIT (1 << UPSR_IE_OFF)
#define UPSR_A20_OFF 6 /* emulation of 1 Mb memory (only for Intel) */
#define UPSR_A20_BIT (1 << UPSR_A20_OFF)
#define UPSR_NMIE_OFF 7 /* not masked interrupt enable */
#define UPSR_NMIE_BIT (1 << UPSR_NMIE_OFF)
/* next field of register exist only on E3S/ES2/E2S/E8C/E1C+ CPUs */
#define UPSR_FSM_OFF 8 /* floating comparison mode flag */
/* 1 - compatible with x86/x87 */
#define UPSR_FSM_BIT (1 << UPSR_FSM_OFF)
#define UPSR_IMPT_OFF 9 /* ignore Memory Protection Table flag */
#define UPSR_IMPT_BIT (1 << UPSR_IMPT_OFF)
#define UPSR_IUC_OFF 10 /* ignore access right for uncached pages */
#define UPSR_IUC_BIT (1 << UPSR_IUC_OFF)
typedef enum {
E2K_EXCP_UNIMPL = 0x01,
E2K_EXCP_SYSCALL = 0x02,
@ -252,6 +277,8 @@ typedef struct CPUArchState {
target_ulong nip; /* next instruction address */
uint32_t upsr;
uint32_t pfpfr; // Packed Floating Point Flag Register (PFPFR)
uint32_t fpcr; // Floating point control register (FPCR)
uint32_t fpsr; // Floating point state register (FPSR)

2
target/e2k/gdbstub.c
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@ -43,7 +43,7 @@ int e2k_cpu_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n)
switch (n) {
case 35: return gdb_get_reg64(mem_buf, 0); // psr
case 36: return gdb_get_reg64(mem_buf, 0); // upsr
case 36: return gdb_get_reg64(mem_buf, env->upsr); // upsr
case 37: return gdb_get_reg64(mem_buf, 0); // oscud_lo
case 38: return gdb_get_reg64(mem_buf, 0); // oscud_hi
case 39: return gdb_get_reg64(mem_buf, 0); // osgd_lo

5
target/e2k/helper.c
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@ -285,6 +285,8 @@ uint64_t helper_state_reg_get(CPUE2KState *env, int reg)
return env->usd_hi;
case 0x2d: /* %usd.lo */
return env->usd_lo;
case 0x80: /* %upsr */
return env->upsr;
case 0x81: /* %ip */
return env->ip;
case 0x83: /* %lsr */
@ -308,6 +310,9 @@ void helper_state_reg_set(CPUE2KState *env, int reg, uint64_t val)
/* FIXME: user cannot write */
env->usd_lo = val;
break;
case 0x80: /* %upsr */
env->upsr = val;
break;
case 0x83: /* %lsr */
env->lsr = val;
break;