Update OHW interface to version 3.
Use common ABI description file with OpenBIOS. git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3648 c046a42c-6fe2-441c-8c8c-71466251a162
This commit is contained in:
blueswir1
parent
57c26279c7
commit
d2c63fc185
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@ -0,0 +1,198 @@
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#ifndef FIRMWARE_ABI_H
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#define FIRMWARE_ABI_H
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#ifndef __ASSEMBLY__
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/* Open Hack'Ware NVRAM configuration structure */
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/* Version 3 */
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typedef struct ohwcfg_v3_t ohwcfg_v3_t;
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struct ohwcfg_v3_t {
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/* 0x00: structure identifier */
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uint8_t struct_ident[0x10];
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/* 0x10: structure version and NVRAM description */
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uint32_t struct_version;
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uint16_t nvram_size;
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uint16_t pad0;
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uint16_t nvram_arch_ptr;
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uint16_t nvram_arch_size;
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uint16_t nvram_arch_crc;
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uint8_t pad1[0x02];
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/* 0x20: host architecture */
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uint8_t arch[0x10];
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/* 0x30: RAM/ROM description */
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uint64_t RAM0_base;
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uint64_t RAM0_size;
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uint64_t RAM1_base;
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uint64_t RAM1_size;
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uint64_t RAM2_base;
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uint64_t RAM2_size;
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uint64_t RAM3_base;
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uint64_t RAM3_size;
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uint64_t ROM_base;
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uint64_t ROM_size;
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/* 0x80: Kernel description */
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uint64_t kernel_image;
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uint64_t kernel_size;
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/* 0x90: Kernel command line */
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uint64_t cmdline;
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uint64_t cmdline_size;
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/* 0xA0: Kernel boot image */
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uint64_t initrd_image;
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uint64_t initrd_size;
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/* 0xB0: NVRAM image */
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uint64_t NVRAM_image;
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uint8_t pad2[8];
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/* 0xC0: graphic configuration */
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uint16_t width;
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uint16_t height;
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uint16_t depth;
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uint16_t graphic_flags;
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/* 0xC8: CPUs description */
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uint8_t nb_cpus;
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uint8_t boot_cpu;
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uint8_t nboot_devices;
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uint8_t pad3[5];
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/* 0xD0: boot devices */
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uint8_t boot_devices[0x10];
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/* 0xE0 */
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uint8_t pad4[0x1C]; /* 28 */
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/* 0xFC: checksum */
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uint16_t crc;
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uint8_t pad5[0x02];
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} __attribute__ (( packed ));
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#define OHW_GF_NOGRAPHICS 0x0001
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static inline uint16_t
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OHW_crc_update (uint16_t prev, uint16_t value)
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{
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uint16_t tmp;
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uint16_t pd, pd1, pd2;
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tmp = prev >> 8;
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pd = prev ^ value;
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pd1 = pd & 0x000F;
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pd2 = ((pd >> 4) & 0x000F) ^ pd1;
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tmp ^= (pd1 << 3) | (pd1 << 8);
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tmp ^= pd2 | (pd2 << 7) | (pd2 << 12);
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return tmp;
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}
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static inline uint16_t
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OHW_compute_crc (ohwcfg_v3_t *header, uint32_t start, uint32_t count)
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{
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uint32_t i;
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uint16_t crc = 0xFFFF;
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uint8_t *ptr = (uint8_t *)header;
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int odd;
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odd = count & 1;
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count &= ~1;
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for (i = 0; i != count; i++) {
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crc = OHW_crc_update(crc, (ptr[start + i] << 8) | ptr[start + i + 1]);
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}
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if (odd) {
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crc = OHW_crc_update(crc, ptr[start + i] << 8);
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}
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return crc;
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}
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/* Sparc32 runtime NVRAM structure for SMP CPU boot */
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struct sparc_arch_cfg {
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uint32_t smp_ctx;
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uint32_t smp_ctxtbl;
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uint32_t smp_entry;
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uint8_t valid;
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uint8_t unused[51];
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};
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/* OpenBIOS NVRAM partition */
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struct OpenBIOS_nvpart_v1 {
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uint8_t signature;
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uint8_t checksum;
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uint16_t len; // BE, length divided by 16
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char name[12];
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};
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#define OPENBIOS_PART_SYSTEM 0x70
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#define OPENBIOS_PART_FREE 0x7f
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static inline void
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OpenBIOS_finish_partition(struct OpenBIOS_nvpart_v1 *header, uint32_t size)
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{
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unsigned int i, sum;
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uint8_t *tmpptr;
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// Length divided by 16
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header->len = cpu_to_be16(size >> 4);
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// Checksum
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tmpptr = (uint8_t *)header;
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sum = *tmpptr;
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for (i = 0; i < 14; i++) {
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sum += tmpptr[2 + i];
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sum = (sum + ((sum & 0xff00) >> 8)) & 0xff;
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}
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header->checksum = sum & 0xff;
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}
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static inline uint32_t
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OpenBIOS_set_var(uint8_t *nvram, uint32_t addr, const unsigned char *str)
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{
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uint32_t len;
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len = strlen(str) + 1;
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memcpy(&nvram[addr], str, len);
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return addr + len;
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}
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/* Sun IDPROM structure at the end of NVRAM */
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struct Sun_nvram {
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uint8_t type;
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uint8_t machine_id;
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uint8_t macaddr[6];
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uint8_t unused[7];
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uint8_t checksum;
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};
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static inline void
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Sun_init_header(struct Sun_nvram *header, const uint8_t *macaddr, int machine_id)
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{
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uint8_t tmp, *tmpptr;
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unsigned int i;
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header->type = 1;
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header->machine_id = machine_id & 0xff;
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memcpy(&header->macaddr, macaddr, 6);
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/* Calculate checksum */
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tmp = 0;
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tmpptr = (uint8_t *)header;
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for (i = 0; i < 15; i++)
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tmp ^= tmpptr[i];
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header->checksum = tmp;
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}
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#else /* __ASSEMBLY__ */
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/* Structure offsets for asm use */
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/* Open Hack'Ware NVRAM configuration structure */
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#define OHW_ARCH_PTR 0x18
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#define OHW_RAM_SIZE 0x38
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#define OHW_BOOT_CPU 0xC9
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/* Sparc32 runtime NVRAM structure for SMP CPU boot */
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#define SPARC_SMP_CTX 0x0
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#define SPARC_SMP_CTXTBL 0x4
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#define SPARC_SMP_ENTRY 0x8
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#define SPARC_SMP_VALID 0xc
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/* Sun IDPROM structure at the end of NVRAM */
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#define SPARC_MACHINE_ID 0x1fd9
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#endif /* __ASSEMBLY__ */
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#endif /* FIRMWARE_ABI_H */
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155
hw/sun4m.c
155
hw/sun4m.c
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@ -22,6 +22,9 @@
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* THE SOFTWARE.
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*/
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#include "vl.h"
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#include "m48t59.h"
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#include "firmware_abi.h"
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//#define DEBUG_IRQ
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/*
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@ -102,131 +105,87 @@ void DMA_register_channel (int nchan,
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{
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}
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static void nvram_set_word (m48t59_t *nvram, uint32_t addr, uint16_t value)
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{
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m48t59_write(nvram, addr++, (value >> 8) & 0xff);
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m48t59_write(nvram, addr++, value & 0xff);
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}
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static void nvram_set_lword (m48t59_t *nvram, uint32_t addr, uint32_t value)
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{
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m48t59_write(nvram, addr++, value >> 24);
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m48t59_write(nvram, addr++, (value >> 16) & 0xff);
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m48t59_write(nvram, addr++, (value >> 8) & 0xff);
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m48t59_write(nvram, addr++, value & 0xff);
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}
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static void nvram_set_string (m48t59_t *nvram, uint32_t addr,
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const unsigned char *str, uint32_t max)
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{
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unsigned int i;
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for (i = 0; i < max && str[i] != '\0'; i++) {
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m48t59_write(nvram, addr + i, str[i]);
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}
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m48t59_write(nvram, addr + max - 1, '\0');
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}
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static uint32_t nvram_set_var (m48t59_t *nvram, uint32_t addr,
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const unsigned char *str)
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{
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uint32_t len;
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len = strlen(str) + 1;
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nvram_set_string(nvram, addr, str, len);
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return addr + len;
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}
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static void nvram_finish_partition (m48t59_t *nvram, uint32_t start,
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uint32_t end)
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{
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unsigned int i, sum;
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// Length divided by 16
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m48t59_write(nvram, start + 2, ((end - start) >> 12) & 0xff);
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m48t59_write(nvram, start + 3, ((end - start) >> 4) & 0xff);
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// Checksum
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sum = m48t59_read(nvram, start);
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for (i = 0; i < 14; i++) {
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sum += m48t59_read(nvram, start + 2 + i);
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sum = (sum + ((sum & 0xff00) >> 8)) & 0xff;
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}
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m48t59_write(nvram, start + 1, sum & 0xff);
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}
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extern int nographic;
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static void nvram_init(m48t59_t *nvram, uint8_t *macaddr, const char *cmdline,
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const char *boot_device, uint32_t RAM_size,
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const char *boot_devices, uint32_t RAM_size,
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uint32_t kernel_size,
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int width, int height, int depth,
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int machine_id)
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{
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unsigned char tmp = 0;
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unsigned int i, j;
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unsigned int i;
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uint32_t start, end;
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uint8_t image[0x1ff0];
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ohwcfg_v3_t *header = (ohwcfg_v3_t *)ℑ
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struct sparc_arch_cfg *sparc_header;
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struct OpenBIOS_nvpart_v1 *part_header;
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memset(image, '\0', sizeof(image));
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// Try to match PPC NVRAM
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nvram_set_string(nvram, 0x00, "QEMU_BIOS", 16);
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nvram_set_lword(nvram, 0x10, 0x00000001); /* structure v1 */
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// NVRAM_size, arch not applicable
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m48t59_write(nvram, 0x2D, smp_cpus & 0xff);
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m48t59_write(nvram, 0x2E, 0);
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m48t59_write(nvram, 0x2F, nographic & 0xff);
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nvram_set_lword(nvram, 0x30, RAM_size);
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m48t59_write(nvram, 0x34, boot_device[0] & 0xff);
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nvram_set_lword(nvram, 0x38, KERNEL_LOAD_ADDR);
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nvram_set_lword(nvram, 0x3C, kernel_size);
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strcpy(header->struct_ident, "QEMU_BIOS");
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header->struct_version = cpu_to_be32(3); /* structure v3 */
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header->nvram_size = cpu_to_be16(0x2000);
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header->nvram_arch_ptr = cpu_to_be16(sizeof(ohwcfg_v3_t));
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header->nvram_arch_size = cpu_to_be16(sizeof(struct sparc_arch_cfg));
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strcpy(header->arch, "sun4m");
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header->nb_cpus = smp_cpus & 0xff;
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header->RAM0_base = 0;
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header->RAM0_size = cpu_to_be64((uint64_t)RAM_size);
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strcpy(header->boot_devices, boot_devices);
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header->nboot_devices = strlen(boot_devices) & 0xff;
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header->kernel_image = cpu_to_be64((uint64_t)KERNEL_LOAD_ADDR);
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header->kernel_size = cpu_to_be64((uint64_t)kernel_size);
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if (cmdline) {
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strcpy(phys_ram_base + CMDLINE_ADDR, cmdline);
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nvram_set_lword(nvram, 0x40, CMDLINE_ADDR);
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nvram_set_lword(nvram, 0x44, strlen(cmdline));
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header->cmdline = cpu_to_be64((uint64_t)CMDLINE_ADDR);
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header->cmdline_size = cpu_to_be64((uint64_t)strlen(cmdline));
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}
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// initrd_image, initrd_size passed differently
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nvram_set_word(nvram, 0x54, width);
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nvram_set_word(nvram, 0x56, height);
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nvram_set_word(nvram, 0x58, depth);
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// XXX add initrd_image, initrd_size
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header->width = cpu_to_be16(width);
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header->height = cpu_to_be16(height);
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header->depth = cpu_to_be16(depth);
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if (nographic)
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header->graphic_flags = cpu_to_be16(OHW_GF_NOGRAPHICS);
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header->crc = cpu_to_be16(OHW_compute_crc(header, 0x00, 0xF8));
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// Architecture specific header
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start = sizeof(ohwcfg_v3_t);
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sparc_header = (struct sparc_arch_cfg *)&image[start];
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sparc_header->valid = 0;
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start += sizeof(struct sparc_arch_cfg);
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// OpenBIOS nvram variables
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// Variable partition
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start = 252;
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m48t59_write(nvram, start, 0x70);
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nvram_set_string(nvram, start + 4, "system", 12);
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part_header = (struct OpenBIOS_nvpart_v1 *)&image[start];
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part_header->signature = OPENBIOS_PART_SYSTEM;
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strcpy(part_header->name, "system");
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end = start + 16;
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end = start + sizeof(struct OpenBIOS_nvpart_v1);
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for (i = 0; i < nb_prom_envs; i++)
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end = nvram_set_var(nvram, end, prom_envs[i]);
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end = OpenBIOS_set_var(image, end, prom_envs[i]);
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// End marker
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image[end++] = '\0';
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m48t59_write(nvram, end++ , 0);
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end = start + ((end - start + 15) & ~15);
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nvram_finish_partition(nvram, start, end);
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OpenBIOS_finish_partition(part_header, end - start);
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// free partition
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start = end;
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m48t59_write(nvram, start, 0x7f);
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nvram_set_string(nvram, start + 4, "free", 12);
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part_header = (struct OpenBIOS_nvpart_v1 *)&image[start];
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part_header->signature = OPENBIOS_PART_FREE;
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strcpy(part_header->name, "free");
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end = 0x1fd0;
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nvram_finish_partition(nvram, start, end);
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OpenBIOS_finish_partition(part_header, end - start);
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// Sun4m specific use
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start = i = 0x1fd8;
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m48t59_write(nvram, i++, 0x01);
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m48t59_write(nvram, i++, machine_id);
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j = 0;
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m48t59_write(nvram, i++, macaddr[j++]);
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m48t59_write(nvram, i++, macaddr[j++]);
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m48t59_write(nvram, i++, macaddr[j++]);
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m48t59_write(nvram, i++, macaddr[j++]);
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m48t59_write(nvram, i++, macaddr[j++]);
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m48t59_write(nvram, i, macaddr[j]);
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Sun_init_header((struct Sun_nvram *)&image[0x1fd8], macaddr, machine_id);
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/* Calculate checksum */
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for (i = start; i < start + 15; i++) {
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tmp ^= m48t59_read(nvram, i);
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}
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m48t59_write(nvram, start + 15, tmp);
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for (i = 0; i < sizeof(image); i++)
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m48t59_write(nvram, i, image[i]);
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}
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static void *slavio_intctl;
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219
hw/sun4u.c
219
hw/sun4u.c
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@ -23,6 +23,7 @@
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*/
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#include "vl.h"
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#include "m48t59.h"
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#include "firmware_abi.h"
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#define KERNEL_LOAD_ADDR 0x00404000
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#define CMDLINE_ADDR 0x003ff000
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@ -66,179 +67,91 @@ void DMA_register_channel (int nchan,
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{
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}
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/* NVRAM helpers */
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static void nvram_set_byte (m48t59_t *nvram, uint32_t addr, uint8_t value)
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{
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m48t59_write(nvram, addr, value);
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}
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static uint8_t nvram_get_byte (m48t59_t *nvram, uint32_t addr)
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{
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return m48t59_read(nvram, addr);
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}
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static void nvram_set_word (m48t59_t *nvram, uint32_t addr, uint16_t value)
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{
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m48t59_write(nvram, addr++, (value >> 8) & 0xff);
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m48t59_write(nvram, addr++, value & 0xff);
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}
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static uint16_t nvram_get_word (m48t59_t *nvram, uint32_t addr)
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{
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uint16_t tmp;
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tmp = m48t59_read(nvram, addr) << 8;
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tmp |= m48t59_read(nvram, addr + 1);
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return tmp;
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}
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static void nvram_set_lword (m48t59_t *nvram, uint32_t addr, uint32_t value)
|
||||
{
|
||||
m48t59_write(nvram, addr++, value >> 24);
|
||||
m48t59_write(nvram, addr++, (value >> 16) & 0xff);
|
||||
m48t59_write(nvram, addr++, (value >> 8) & 0xff);
|
||||
m48t59_write(nvram, addr++, value & 0xff);
|
||||
}
|
||||
|
||||
static void nvram_set_string (m48t59_t *nvram, uint32_t addr,
|
||||
const unsigned char *str, uint32_t max)
|
||||
{
|
||||
unsigned int i;
|
||||
|
||||
for (i = 0; i < max && str[i] != '\0'; i++) {
|
||||
m48t59_write(nvram, addr + i, str[i]);
|
||||
}
|
||||
m48t59_write(nvram, addr + max - 1, '\0');
|
||||
}
|
||||
|
||||
static uint16_t nvram_crc_update (uint16_t prev, uint16_t value)
|
||||
{
|
||||
uint16_t tmp;
|
||||
uint16_t pd, pd1, pd2;
|
||||
|
||||
tmp = prev >> 8;
|
||||
pd = prev ^ value;
|
||||
pd1 = pd & 0x000F;
|
||||
pd2 = ((pd >> 4) & 0x000F) ^ pd1;
|
||||
tmp ^= (pd1 << 3) | (pd1 << 8);
|
||||
tmp ^= pd2 | (pd2 << 7) | (pd2 << 12);
|
||||
|
||||
return tmp;
|
||||
}
|
||||
|
||||
static uint16_t nvram_compute_crc (m48t59_t *nvram, uint32_t start,
|
||||
uint32_t count)
|
||||
{
|
||||
uint32_t i;
|
||||
uint16_t crc = 0xFFFF;
|
||||
int odd;
|
||||
|
||||
odd = count & 1;
|
||||
count &= ~1;
|
||||
for (i = 0; i != count; i++) {
|
||||
crc = nvram_crc_update(crc, nvram_get_word(nvram, start + i));
|
||||
}
|
||||
if (odd) {
|
||||
crc = nvram_crc_update(crc, nvram_get_byte(nvram, start + i) << 8);
|
||||
}
|
||||
|
||||
return crc;
|
||||
}
|
||||
|
||||
static uint32_t nvram_set_var (m48t59_t *nvram, uint32_t addr,
|
||||
const unsigned char *str)
|
||||
{
|
||||
uint32_t len;
|
||||
|
||||
len = strlen(str) + 1;
|
||||
nvram_set_string(nvram, addr, str, len);
|
||||
|
||||
return addr + len;
|
||||
}
|
||||
|
||||
static void nvram_finish_partition (m48t59_t *nvram, uint32_t start,
|
||||
uint32_t end)
|
||||
{
|
||||
unsigned int i, sum;
|
||||
|
||||
// Length divided by 16
|
||||
m48t59_write(nvram, start + 2, ((end - start) >> 12) & 0xff);
|
||||
m48t59_write(nvram, start + 3, ((end - start) >> 4) & 0xff);
|
||||
// Checksum
|
||||
sum = m48t59_read(nvram, start);
|
||||
for (i = 0; i < 14; i++) {
|
||||
sum += m48t59_read(nvram, start + 2 + i);
|
||||
sum = (sum + ((sum & 0xff00) >> 8)) & 0xff;
|
||||
}
|
||||
m48t59_write(nvram, start + 1, sum & 0xff);
|
||||
}
|
||||
|
||||
extern int nographic;
|
||||
|
||||
int sun4u_NVRAM_set_params (m48t59_t *nvram, uint16_t NVRAM_size,
|
||||
const unsigned char *arch,
|
||||
uint32_t RAM_size, int boot_device,
|
||||
uint32_t kernel_image, uint32_t kernel_size,
|
||||
const char *cmdline,
|
||||
uint32_t initrd_image, uint32_t initrd_size,
|
||||
uint32_t NVRAM_image,
|
||||
int width, int height, int depth)
|
||||
static int sun4u_NVRAM_set_params (m48t59_t *nvram, uint16_t NVRAM_size,
|
||||
const unsigned char *arch,
|
||||
uint32_t RAM_size, const char *boot_devices,
|
||||
uint32_t kernel_image, uint32_t kernel_size,
|
||||
const char *cmdline,
|
||||
uint32_t initrd_image, uint32_t initrd_size,
|
||||
uint32_t NVRAM_image,
|
||||
int width, int height, int depth)
|
||||
{
|
||||
uint16_t crc;
|
||||
unsigned int i;
|
||||
uint32_t start, end;
|
||||
uint8_t image[0x1ff0];
|
||||
ohwcfg_v3_t *header = (ohwcfg_v3_t *)ℑ
|
||||
struct sparc_arch_cfg *sparc_header;
|
||||
struct OpenBIOS_nvpart_v1 *part_header;
|
||||
|
||||
/* Set parameters for Open Hack'Ware BIOS */
|
||||
nvram_set_string(nvram, 0x00, "QEMU_BIOS", 16);
|
||||
nvram_set_lword(nvram, 0x10, 0x00000002); /* structure v2 */
|
||||
nvram_set_word(nvram, 0x14, NVRAM_size);
|
||||
nvram_set_string(nvram, 0x20, arch, 16);
|
||||
nvram_set_byte(nvram, 0x2f, nographic & 0xff);
|
||||
nvram_set_lword(nvram, 0x30, RAM_size);
|
||||
nvram_set_byte(nvram, 0x34, boot_device);
|
||||
nvram_set_lword(nvram, 0x38, kernel_image);
|
||||
nvram_set_lword(nvram, 0x3C, kernel_size);
|
||||
memset(image, '\0', sizeof(image));
|
||||
|
||||
// Try to match PPC NVRAM
|
||||
strcpy(header->struct_ident, "QEMU_BIOS");
|
||||
header->struct_version = cpu_to_be32(3); /* structure v3 */
|
||||
|
||||
header->nvram_size = cpu_to_be16(NVRAM_size);
|
||||
header->nvram_arch_ptr = cpu_to_be16(sizeof(ohwcfg_v3_t));
|
||||
header->nvram_arch_size = cpu_to_be16(sizeof(struct sparc_arch_cfg));
|
||||
strcpy(header->arch, arch);
|
||||
header->nb_cpus = smp_cpus & 0xff;
|
||||
header->RAM0_base = 0;
|
||||
header->RAM0_size = cpu_to_be64((uint64_t)RAM_size);
|
||||
strcpy(header->boot_devices, boot_devices);
|
||||
header->nboot_devices = strlen(boot_devices) & 0xff;
|
||||
header->kernel_image = cpu_to_be64((uint64_t)kernel_image);
|
||||
header->kernel_size = cpu_to_be64((uint64_t)kernel_size);
|
||||
if (cmdline) {
|
||||
/* XXX: put the cmdline in NVRAM too ? */
|
||||
strcpy(phys_ram_base + CMDLINE_ADDR, cmdline);
|
||||
nvram_set_lword(nvram, 0x40, CMDLINE_ADDR);
|
||||
nvram_set_lword(nvram, 0x44, strlen(cmdline));
|
||||
} else {
|
||||
nvram_set_lword(nvram, 0x40, 0);
|
||||
nvram_set_lword(nvram, 0x44, 0);
|
||||
header->cmdline = cpu_to_be64((uint64_t)CMDLINE_ADDR);
|
||||
header->cmdline_size = cpu_to_be64((uint64_t)strlen(cmdline));
|
||||
}
|
||||
nvram_set_lword(nvram, 0x48, initrd_image);
|
||||
nvram_set_lword(nvram, 0x4C, initrd_size);
|
||||
nvram_set_lword(nvram, 0x50, NVRAM_image);
|
||||
header->initrd_image = cpu_to_be64((uint64_t)initrd_image);
|
||||
header->initrd_size = cpu_to_be64((uint64_t)initrd_size);
|
||||
header->NVRAM_image = cpu_to_be64((uint64_t)NVRAM_image);
|
||||
|
||||
nvram_set_word(nvram, 0x54, width);
|
||||
nvram_set_word(nvram, 0x56, height);
|
||||
nvram_set_word(nvram, 0x58, depth);
|
||||
crc = nvram_compute_crc(nvram, 0x00, 0xF8);
|
||||
nvram_set_word(nvram, 0xFC, crc);
|
||||
header->width = cpu_to_be16(width);
|
||||
header->height = cpu_to_be16(height);
|
||||
header->depth = cpu_to_be16(depth);
|
||||
if (nographic)
|
||||
header->graphic_flags = cpu_to_be16(OHW_GF_NOGRAPHICS);
|
||||
|
||||
header->crc = cpu_to_be16(OHW_compute_crc(header, 0x00, 0xF8));
|
||||
|
||||
// Architecture specific header
|
||||
start = sizeof(ohwcfg_v3_t);
|
||||
sparc_header = (struct sparc_arch_cfg *)&image[start];
|
||||
sparc_header->valid = 0;
|
||||
start += sizeof(struct sparc_arch_cfg);
|
||||
|
||||
// OpenBIOS nvram variables
|
||||
// Variable partition
|
||||
start = 256;
|
||||
m48t59_write(nvram, start, 0x70);
|
||||
nvram_set_string(nvram, start + 4, "system", 12);
|
||||
part_header = (struct OpenBIOS_nvpart_v1 *)&image[start];
|
||||
part_header->signature = OPENBIOS_PART_SYSTEM;
|
||||
strcpy(part_header->name, "system");
|
||||
|
||||
end = start + 16;
|
||||
end = start + sizeof(struct OpenBIOS_nvpart_v1);
|
||||
for (i = 0; i < nb_prom_envs; i++)
|
||||
end = nvram_set_var(nvram, end, prom_envs[i]);
|
||||
end = OpenBIOS_set_var(image, end, prom_envs[i]);
|
||||
|
||||
// End marker
|
||||
image[end++] = '\0';
|
||||
|
||||
m48t59_write(nvram, end++ , 0);
|
||||
end = start + ((end - start + 15) & ~15);
|
||||
nvram_finish_partition(nvram, start, end);
|
||||
OpenBIOS_finish_partition(part_header, end - start);
|
||||
|
||||
// free partition
|
||||
start = end;
|
||||
m48t59_write(nvram, start, 0x7f);
|
||||
nvram_set_string(nvram, start + 4, "free", 12);
|
||||
part_header = (struct OpenBIOS_nvpart_v1 *)&image[start];
|
||||
part_header->signature = OPENBIOS_PART_FREE;
|
||||
strcpy(part_header->name, "free");
|
||||
|
||||
end = 0x1fd0;
|
||||
nvram_finish_partition(nvram, start, end);
|
||||
OpenBIOS_finish_partition(part_header, end - start);
|
||||
|
||||
for (i = 0; i < sizeof(image); i++)
|
||||
m48t59_write(nvram, i, image[i]);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
|
@ -306,7 +219,7 @@ static const int parallel_irq[MAX_PARALLEL_PORTS] = { 7, 7, 7 };
|
|||
static fdctrl_t *floppy_controller;
|
||||
|
||||
/* Sun4u hardware initialisation */
|
||||
static void sun4u_init(int ram_size, int vga_ram_size, const char *boot_device,
|
||||
static void sun4u_init(int ram_size, int vga_ram_size, const char *boot_devices,
|
||||
DisplayState *ds, const char **fd_filename, int snapshot,
|
||||
const char *kernel_filename, const char *kernel_cmdline,
|
||||
const char *initrd_filename, const char *cpu_model)
|
||||
|
|
@ -428,7 +341,7 @@ static void sun4u_init(int ram_size, int vga_ram_size, const char *boot_device,
|
|||
i8042_init(NULL/*1*/, NULL/*12*/, 0x60);
|
||||
floppy_controller = fdctrl_init(NULL/*6*/, 2, 0, 0x3f0, fd_table);
|
||||
nvram = m48t59_init(NULL/*8*/, 0, 0x0074, NVRAM_SIZE, 59);
|
||||
sun4u_NVRAM_set_params(nvram, NVRAM_SIZE, "Sun4u", ram_size, boot_device[0],
|
||||
sun4u_NVRAM_set_params(nvram, NVRAM_SIZE, "Sun4u", ram_size, boot_devices,
|
||||
KERNEL_LOAD_ADDR, kernel_size,
|
||||
kernel_cmdline,
|
||||
INITRD_LOAD_ADDR, initrd_size,
|
||||
|
|
|
|||
Loading…
Reference in New Issue