tcg/riscv: Fix illegal shift instructions
Out-of-range shifts have undefined results, but must not trap. Mask off immediate shift counts to solve this problem. This bug can be reproduced by running the following guest instructions: xor %ecx,%ecx sar %cl,%eax cmovne %edi,%eax After optimization, the tcg opcodes of the sar are movi_i32 tmp3,$0xffffffffffffffff pref=all sar_i32 tmp3,eax,tmp3 dead: 2 pref=all mov_i32 cc_dst,eax sync: 0 dead: 1 pref=0xffc0300 mov_i32 cc_src,tmp3 sync: 0 dead: 0 1 pref=all movi_i32 cc_op,$0x31 sync: 0 dead: 0 pref=all The sar_i32 opcode is a shift by -1, which unmasked generates 0x200808d618: fffa5b9b illegal Signed-off-by: Zihao Yu <yuzihao@ict.ac.cn> Message-Id: <20201216081206.9628-1-yuzihao@ict.ac.cn> [rth: Reworded the patch description.] Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
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@ -1462,14 +1462,14 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc,
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case INDEX_op_shl_i32:
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if (c2) {
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tcg_out_opc_imm(s, OPC_SLLIW, a0, a1, a2);
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tcg_out_opc_imm(s, OPC_SLLIW, a0, a1, a2 & 0x1f);
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} else {
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tcg_out_opc_reg(s, OPC_SLLW, a0, a1, a2);
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}
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break;
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case INDEX_op_shl_i64:
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if (c2) {
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tcg_out_opc_imm(s, OPC_SLLI, a0, a1, a2);
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tcg_out_opc_imm(s, OPC_SLLI, a0, a1, a2 & 0x3f);
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} else {
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tcg_out_opc_reg(s, OPC_SLL, a0, a1, a2);
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}
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@ -1477,14 +1477,14 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc,
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case INDEX_op_shr_i32:
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if (c2) {
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tcg_out_opc_imm(s, OPC_SRLIW, a0, a1, a2);
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tcg_out_opc_imm(s, OPC_SRLIW, a0, a1, a2 & 0x1f);
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} else {
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tcg_out_opc_reg(s, OPC_SRLW, a0, a1, a2);
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}
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break;
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case INDEX_op_shr_i64:
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if (c2) {
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tcg_out_opc_imm(s, OPC_SRLI, a0, a1, a2);
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tcg_out_opc_imm(s, OPC_SRLI, a0, a1, a2 & 0x3f);
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} else {
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tcg_out_opc_reg(s, OPC_SRL, a0, a1, a2);
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}
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@ -1492,14 +1492,14 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc,
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case INDEX_op_sar_i32:
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if (c2) {
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tcg_out_opc_imm(s, OPC_SRAIW, a0, a1, a2);
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tcg_out_opc_imm(s, OPC_SRAIW, a0, a1, a2 & 0x1f);
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} else {
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tcg_out_opc_reg(s, OPC_SRAW, a0, a1, a2);
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}
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break;
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case INDEX_op_sar_i64:
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if (c2) {
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tcg_out_opc_imm(s, OPC_SRAI, a0, a1, a2);
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tcg_out_opc_imm(s, OPC_SRAI, a0, a1, a2 & 0x3f);
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} else {
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tcg_out_opc_reg(s, OPC_SRA, a0, a1, a2);
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}
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