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nios2: Add IIC interrupt controller emulation

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Add the Altera Nios2 internal interrupt controller model.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chris Wulff <crwulff@gmail.com>
Cc: Jeff Da Silva <jdasilva@altera.com>
Cc: Ley Foon Tan <lftan@altera.com>
Cc: Sandra Loosemore <sandra@codesourcery.com>
Cc: Yves Vandervennet <yvanderv@altera.com>
Reviewed-by: Alexander Graf <agraf@suse.de>
Message-Id: <20170118220146.489-5-marex@denx.de>
Signed-off-by: Richard Henderson <rth@twiddle.net>
This commit is contained in:
Chris Wulff 2017-01-18 23:01:43 +01:00 committed by Richard Henderson
parent a0a839b65b
commit d2fe4ec19d
2 changed files with 104 additions and 0 deletions
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1
hw/intc/Makefile.objs
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@ -41,3 +41,4 @@ obj-$(CONFIG_S390_FLIC_KVM) += s390_flic_kvm.o
obj-$(CONFIG_ASPEED_SOC) += aspeed_vic.o
obj-$(CONFIG_ARM_GIC) += arm_gicv3_cpuif.o
obj-$(CONFIG_MIPS_CPS) += mips_gic.o
obj-$(CONFIG_NIOS2) += nios2_iic.o

103
hw/intc/nios2_iic.c Normal file
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@ -0,0 +1,103 @@
/*
* QEMU Altera Internal Interrupt Controller.
*
* Copyright (c) 2012 Chris Wulff <crwulff@gmail.com>
*
* This library is free software; you can redistribute it and/or
* modify it under the terms of the GNU Lesser General Public
* License as published by the Free Software Foundation; either
* version 2.1 of the License, or (at your option) any later version.
*
* This library is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
* Lesser General Public License for more details.
*
* You should have received a copy of the GNU Lesser General Public
* License along with this library; if not, see
* <http://www.gnu.org/licenses/lgpl-2.1.html>
*/
#include "qemu/osdep.h"
#include "qemu-common.h"
#include "qapi/error.h"
#include "hw/sysbus.h"
#include "cpu.h"
#define TYPE_ALTERA_IIC "altera,iic"
#define ALTERA_IIC(obj) \
OBJECT_CHECK(AlteraIIC, (obj), TYPE_ALTERA_IIC)
typedef struct AlteraIIC {
SysBusDevice parent_obj;
void *cpu;
qemu_irq parent_irq;
} AlteraIIC;
static void update_irq(AlteraIIC *pv)
{
CPUNios2State *env = &((Nios2CPU *)(pv->cpu))->env;
qemu_set_irq(pv->parent_irq,
env->regs[CR_IPENDING] & env->regs[CR_IENABLE]);
}
static void irq_handler(void *opaque, int irq, int level)
{
AlteraIIC *pv = opaque;
CPUNios2State *env = &((Nios2CPU *)(pv->cpu))->env;
env->regs[CR_IPENDING] &= ~(1 << irq);
env->regs[CR_IPENDING] |= !!level << irq;
update_irq(pv);
}
static void altera_iic_init(Object *obj)
{
AlteraIIC *pv = ALTERA_IIC(obj);
qdev_init_gpio_in(DEVICE(pv), irq_handler, 32);
sysbus_init_irq(SYS_BUS_DEVICE(obj), &pv->parent_irq);
}
static Property altera_iic_properties[] = {
DEFINE_PROP_PTR("cpu", AlteraIIC, cpu),
DEFINE_PROP_END_OF_LIST(),
};
static void altera_iic_realize(DeviceState *dev, Error **errp)
{
struct AlteraIIC *pv = ALTERA_IIC(dev);
if (!pv->cpu) {
error_setg(errp, "altera,iic: CPU not connected");
return;
}
}
static void altera_iic_class_init(ObjectClass *klass, void *data)
{
DeviceClass *dc = DEVICE_CLASS(klass);
dc->props = altera_iic_properties;
/* Reason: pointer property "cpu" */
dc->cannot_instantiate_with_device_add_yet = true;
dc->realize = altera_iic_realize;
}
static TypeInfo altera_iic_info = {
.name = "altera,iic",
.parent = TYPE_SYS_BUS_DEVICE,
.instance_size = sizeof(AlteraIIC),
.instance_init = altera_iic_init,
.class_init = altera_iic_class_init,
};
static void altera_iic_register(void)
{
type_register_static(&altera_iic_info);
}
type_init(altera_iic_register)