target/ppc: Implement DCFFIXQQ
Implement the following PowerISA v3.1 instruction: dcffixqq: DFP Convert From Fixed Quadword Quad Signed-off-by: Luis Pires <luis.pires@eldorado.org.br> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20211029192417.400707-5-luis.pires@eldorado.org.br> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
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@ -970,6 +970,18 @@ static void CFFIX_PPs(struct PPC_DFP *dfp)
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DFP_HELPER_CFFIX(dcffix, 64)
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DFP_HELPER_CFFIX(dcffix, 64)
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DFP_HELPER_CFFIX(dcffixq, 128)
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DFP_HELPER_CFFIX(dcffixq, 128)
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void helper_DCFFIXQQ(CPUPPCState *env, ppc_fprp_t *t, ppc_avr_t *b)
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{
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struct PPC_DFP dfp;
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dfp_prepare_decimal128(&dfp, NULL, NULL, env);
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decNumberFromInt128(&dfp.t, (uint64_t)b->VsrD(1), (int64_t)b->VsrD(0));
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dfp_finalize_decimal128(&dfp);
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CFFIX_PPs(&dfp);
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set_dfp128(t, &dfp.vt);
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}
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#define DFP_HELPER_CTFIX(op, size) \
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#define DFP_HELPER_CTFIX(op, size) \
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void helper_##op(CPUPPCState *env, ppc_fprp_t *t, ppc_fprp_t *b) \
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void helper_##op(CPUPPCState *env, ppc_fprp_t *t, ppc_fprp_t *b) \
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{ \
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{ \
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@ -736,6 +736,7 @@ DEF_HELPER_3(drsp, void, env, fprp, fprp)
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DEF_HELPER_3(drdpq, void, env, fprp, fprp)
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DEF_HELPER_3(drdpq, void, env, fprp, fprp)
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DEF_HELPER_3(dcffix, void, env, fprp, fprp)
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DEF_HELPER_3(dcffix, void, env, fprp, fprp)
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DEF_HELPER_3(dcffixq, void, env, fprp, fprp)
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DEF_HELPER_3(dcffixq, void, env, fprp, fprp)
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DEF_HELPER_3(DCFFIXQQ, void, env, fprp, avr)
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DEF_HELPER_3(dctfix, void, env, fprp, fprp)
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DEF_HELPER_3(dctfix, void, env, fprp, fprp)
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DEF_HELPER_3(dctfixq, void, env, fprp, fprp)
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DEF_HELPER_3(dctfixq, void, env, fprp, fprp)
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DEF_HELPER_4(ddedpd, void, env, fprp, fprp, i32)
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DEF_HELPER_4(ddedpd, void, env, fprp, fprp, i32)
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@ -50,6 +50,10 @@
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&X_bfl bf l:bool ra rb
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&X_bfl bf l:bool ra rb
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@X_bfl ...... bf:3 - l:1 ra:5 rb:5 ..........- &X_bfl
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@X_bfl ...... bf:3 - l:1 ra:5 rb:5 ..........- &X_bfl
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&X_frtp_vrb frtp vrb
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%x_frtp 22:4 !function=times_2
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@X_frtp_vrb ...... ....0 ..... vrb:5 .......... . &X_frtp_vrb frtp=%x_frtp
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### Fixed-Point Load Instructions
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### Fixed-Point Load Instructions
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LBZ 100010 ..... ..... ................ @D
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LBZ 100010 ..... ..... ................ @D
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@ -160,6 +164,10 @@ SETBCR 011111 ..... ..... ----- 0110100000 - @X_bi
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SETNBC 011111 ..... ..... ----- 0111000000 - @X_bi
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SETNBC 011111 ..... ..... ----- 0111000000 - @X_bi
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SETNBCR 011111 ..... ..... ----- 0111100000 - @X_bi
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SETNBCR 011111 ..... ..... ----- 0111100000 - @X_bi
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### Decimal Floating-Point Conversion Instructions
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DCFFIXQQ 111111 ..... 00000 ..... 1111100010 - @X_frtp_vrb
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## Vector Bit Manipulation Instruction
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## Vector Bit Manipulation Instruction
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VCFUGED 000100 ..... ..... ..... 10101001101 @VX
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VCFUGED 000100 ..... ..... ..... 10101001101 @VX
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@ -7305,6 +7305,11 @@ static inline void set_avr64(int regno, TCGv_i64 src, bool high)
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/*
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/*
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* Helpers for decodetree used by !function for decoding arguments.
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* Helpers for decodetree used by !function for decoding arguments.
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*/
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*/
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static int times_2(DisasContext *ctx, int x)
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{
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return x * 2;
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}
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static int times_4(DisasContext *ctx, int x)
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static int times_4(DisasContext *ctx, int x)
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{
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{
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return x * 4;
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return x * 4;
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@ -230,3 +230,20 @@ GEN_DFP_T_FPR_I32_Rc(dscriq, rA, DCM)
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#undef GEN_DFP_T_A_B_I32_Rc
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#undef GEN_DFP_T_A_B_I32_Rc
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#undef GEN_DFP_T_B_Rc
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#undef GEN_DFP_T_B_Rc
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#undef GEN_DFP_T_FPR_I32_Rc
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#undef GEN_DFP_T_FPR_I32_Rc
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static bool trans_DCFFIXQQ(DisasContext *ctx, arg_DCFFIXQQ *a)
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{
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TCGv_ptr rt, rb;
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REQUIRE_INSNS_FLAGS2(ctx, DFP);
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REQUIRE_FPU(ctx);
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REQUIRE_VECTOR(ctx);
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rt = gen_fprp_ptr(a->frtp);
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rb = gen_avr_ptr(a->vrb);
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gen_helper_DCFFIXQQ(cpu_env, rt, rb);
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tcg_temp_free_ptr(rt);
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tcg_temp_free_ptr(rb);
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return true;
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}
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