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hw/i386/pc: Extract the port92 device

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This device is only used by the PC machines. The pc.c file is
already big enough, with 2255 lines. By removing 113 lines of
it, we reduced it by 5%. It is now a bit easier to navigate
the file.

Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
This commit is contained in:
Philippe Mathieu-Daudé 2019-12-13 11:51:00 +01:00 committed by Paolo Bonzini
parent 1820b70eb3
commit d3e07dc83e
5 changed files with 131 additions and 114 deletions
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1
hw/i386/Makefile.objs
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@ -13,6 +13,7 @@ obj-$(CONFIG_AMD_IOMMU) += amd_iommu.o
obj-$(CONFIG_XEN) += ../xenpv/ xen/
obj-$(CONFIG_VMPORT) += vmport.o
obj-$(CONFIG_VMMOUSE) += vmmouse.o
obj-$(CONFIG_PC) += port92.o
obj-y += kvmvapic.o
obj-$(CONFIG_PC) += acpi-build.o

113
hw/i386/pc.c
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@ -673,119 +673,6 @@ void pc_cmos_init(PCMachineState *pcms,
qemu_register_reset(pc_cmos_init_late, &arg);
}
#define TYPE_PORT92 "port92"
#define PORT92(obj) OBJECT_CHECK(Port92State, (obj), TYPE_PORT92)
/* port 92 stuff: could be split off */
typedef struct Port92State {
ISADevice parent_obj;
MemoryRegion io;
uint8_t outport;
qemu_irq a20_out;
} Port92State;
static void port92_write(void *opaque, hwaddr addr, uint64_t val,
unsigned size)
{
Port92State *s = opaque;
int oldval = s->outport;
trace_port92_write(val);
s->outport = val;
qemu_set_irq(s->a20_out, (val >> 1) & 1);
if ((val & 1) && !(oldval & 1)) {
qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET);
}
}
static uint64_t port92_read(void *opaque, hwaddr addr,
unsigned size)
{
Port92State *s = opaque;
uint32_t ret;
ret = s->outport;
trace_port92_read(ret);
return ret;
}
static const VMStateDescription vmstate_port92_isa = {
.name = "port92",
.version_id = 1,
.minimum_version_id = 1,
.fields = (VMStateField[]) {
VMSTATE_UINT8(outport, Port92State),
VMSTATE_END_OF_LIST()
}
};
static void port92_reset(DeviceState *d)
{
Port92State *s = PORT92(d);
s->outport &= ~1;
}
static const MemoryRegionOps port92_ops = {
.read = port92_read,
.write = port92_write,
.impl = {
.min_access_size = 1,
.max_access_size = 1,
},
.endianness = DEVICE_LITTLE_ENDIAN,
};
static void port92_initfn(Object *obj)
{
Port92State *s = PORT92(obj);
memory_region_init_io(&s->io, OBJECT(s), &port92_ops, s, "port92", 1);
s->outport = 0;
qdev_init_gpio_out_named(DEVICE(obj), &s->a20_out, PORT92_A20_LINE, 1);
}
static void port92_realizefn(DeviceState *dev, Error **errp)
{
ISADevice *isadev = ISA_DEVICE(dev);
Port92State *s = PORT92(dev);
isa_register_ioport(isadev, &s->io, 0x92);
}
static void port92_class_initfn(ObjectClass *klass, void *data)
{
DeviceClass *dc = DEVICE_CLASS(klass);
dc->realize = port92_realizefn;
dc->reset = port92_reset;
dc->vmsd = &vmstate_port92_isa;
/*
* Reason: unlike ordinary ISA devices, this one needs additional
* wiring: its A20 output line needs to be wired up with
* qdev_connect_gpio_out_named().
*/
dc->user_creatable = false;
}
static const TypeInfo port92_info = {
.name = TYPE_PORT92,
.parent = TYPE_ISA_DEVICE,
.instance_size = sizeof(Port92State),
.instance_init = port92_initfn,
.class_init = port92_class_initfn,
};
static void port92_register_types(void)
{
type_register_static(&port92_info);
}
type_init(port92_register_types)
static void handle_a20_line_change(void *opaque, int irq, int level)
{
X86CPU *cpu = opaque;

126
hw/i386/port92.c Normal file
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@ -0,0 +1,126 @@
/*
* QEMU I/O port 0x92 (System Control Port A, to handle Fast Gate A20)
*
* Copyright (c) 2003-2004 Fabrice Bellard
*
* SPDX-License-Identifier: MIT
*/
#include "qemu/osdep.h"
#include "sysemu/runstate.h"
#include "migration/vmstate.h"
#include "hw/irq.h"
#include "hw/i386/pc.h"
#include "trace.h"
#define PORT92(obj) OBJECT_CHECK(Port92State, (obj), TYPE_PORT92)
typedef struct Port92State {
ISADevice parent_obj;
MemoryRegion io;
uint8_t outport;
qemu_irq a20_out;
} Port92State;
static void port92_write(void *opaque, hwaddr addr, uint64_t val,
unsigned size)
{
Port92State *s = opaque;
int oldval = s->outport;
trace_port92_write(val);
s->outport = val;
qemu_set_irq(s->a20_out, (val >> 1) & 1);
if ((val & 1) && !(oldval & 1)) {
qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET);
}
}
static uint64_t port92_read(void *opaque, hwaddr addr,
unsigned size)
{
Port92State *s = opaque;
uint32_t ret;
ret = s->outport;
trace_port92_read(ret);
return ret;
}
static const VMStateDescription vmstate_port92_isa = {
.name = "port92",
.version_id = 1,
.minimum_version_id = 1,
.fields = (VMStateField[]) {
VMSTATE_UINT8(outport, Port92State),
VMSTATE_END_OF_LIST()
}
};
static void port92_reset(DeviceState *d)
{
Port92State *s = PORT92(d);
s->outport &= ~1;
}
static const MemoryRegionOps port92_ops = {
.read = port92_read,
.write = port92_write,
.impl = {
.min_access_size = 1,
.max_access_size = 1,
},
.endianness = DEVICE_LITTLE_ENDIAN,
};
static void port92_initfn(Object *obj)
{
Port92State *s = PORT92(obj);
memory_region_init_io(&s->io, OBJECT(s), &port92_ops, s, "port92", 1);
s->outport = 0;
qdev_init_gpio_out_named(DEVICE(obj), &s->a20_out, PORT92_A20_LINE, 1);
}
static void port92_realizefn(DeviceState *dev, Error **errp)
{
ISADevice *isadev = ISA_DEVICE(dev);
Port92State *s = PORT92(dev);
isa_register_ioport(isadev, &s->io, 0x92);
}
static void port92_class_initfn(ObjectClass *klass, void *data)
{
DeviceClass *dc = DEVICE_CLASS(klass);
dc->realize = port92_realizefn;
dc->reset = port92_reset;
dc->vmsd = &vmstate_port92_isa;
/*
* Reason: unlike ordinary ISA devices, this one needs additional
* wiring: its A20 output line needs to be wired up with
* qdev_connect_gpio_out_named().
*/
dc->user_creatable = false;
}
static const TypeInfo port92_info = {
.name = TYPE_PORT92,
.parent = TYPE_ISA_DEVICE,
.instance_size = sizeof(Port92State),
.instance_init = port92_initfn,
.class_init = port92_class_initfn,
};
static void port92_register_types(void)
{
type_register_static(&port92_info);
}
type_init(port92_register_types)

2
hw/i386/trace-events
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@ -116,6 +116,6 @@ vmport_command(unsigned char command) "command: 0x%02x"
x86_gsi_interrupt(int irqn, int level) "GSI interrupt #%d level:%d"
x86_pic_interrupt(int irqn, int level) "PIC interrupt #%d level:%d"
# pc.c
# port92.c
port92_read(uint8_t val) "port92: read 0x%02x"
port92_write(uint8_t val) "port92: write 0x%02x"

3
include/hw/i386/pc.h
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@ -196,8 +196,11 @@ void pc_i8259_create(ISABus *isa_bus, qemu_irq *i8259_irqs);
ISADevice *pc_find_fdc0(void);
int cmos_get_fd_drive_type(FloppyDriveType fd0);
/* port92.c */
#define PORT92_A20_LINE "a20"
#define TYPE_PORT92 "port92"
/* pc_sysfw.c */
void pc_system_flash_create(PCMachineState *pcms);
void pc_system_firmware_init(PCMachineState *pcms, MemoryRegion *rom_memory);