From d4ea71170432fef9e8394ab33eac3cdc3a9540d3 Mon Sep 17 00:00:00 2001 From: Daniel Henrique Barboza Date: Wed, 22 Feb 2023 15:51:56 -0300 Subject: [PATCH 01/10] target/riscv: introduce riscv_cpu_cfg() We're going to do changes that requires accessing the RISCVCPUConfig struct from the RISCVCPU, having access only to a CPURISCVState 'env' pointer. Add a helper to make the code easier to read. Signed-off-by: Daniel Henrique Barboza Reviewed-by: Bin Meng Reviewed-by: LIU Zhiwei Reviewed-by: Weiwei Li Reviewed-by: Richard Henderson Message-ID: <20230222185205.355361-2-dbarboza@ventanamicro.com> Signed-off-by: Palmer Dabbelt --- target/riscv/cpu.h | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 31537fc05f..7ee22cbfa1 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -654,6 +654,11 @@ static inline RISCVMXL riscv_cpu_mxl(CPURISCVState *env) #endif #define riscv_cpu_mxl_bits(env) (1UL << (4 + riscv_cpu_mxl(env))) +static inline const RISCVCPUConfig *riscv_cpu_cfg(CPURISCVState *env) +{ + return &env_archcpu(env)->cfg; +} + #if defined(TARGET_RISCV32) #define cpu_recompute_xl(env) ((void)(env), MXL_RV32) #else From 5b17fefb90adcd79854858b2671106ad1035b391 Mon Sep 17 00:00:00 2001 From: Daniel Henrique Barboza Date: Wed, 22 Feb 2023 15:51:57 -0300 Subject: [PATCH 02/10] target/riscv: do not mask unsupported QEMU extensions in write_misa() The masking done using env->misa_ext_mask already filters any extension that QEMU doesn't support. If the hart supports the extension then QEMU supports it as well. If the masking done by env->misa_ext_mask is somehow letting unsupported QEMU extensions pass by, misa_ext_mask itself needs to be fixed instead. Signed-off-by: Daniel Henrique Barboza Reviewed-by: Weiwei Li Reviewed-by: Bin Meng Reviewed-by: Andrew Jones Message-ID: <20230222185205.355361-3-dbarboza@ventanamicro.com> Signed-off-by: Palmer Dabbelt --- target/riscv/csr.c | 3 --- 1 file changed, 3 deletions(-) diff --git a/target/riscv/csr.c b/target/riscv/csr.c index 1b0a0c1693..e149b453da 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -1356,9 +1356,6 @@ static RISCVException write_misa(CPURISCVState *env, int csrno, /* Mask extensions that are not supported by this hart */ val &= env->misa_ext_mask; - /* Mask extensions that are not supported by QEMU */ - val &= (RVI | RVE | RVM | RVA | RVF | RVD | RVC | RVS | RVU | RVV); - /* 'D' depends on 'F', so clear 'D' if 'F' is not present */ if ((val & RVD) && !(val & RVF)) { val &= ~RVD; From 54bd9b6ec3d67d3825258ef1fc3cec8f9679bdd5 Mon Sep 17 00:00:00 2001 From: Daniel Henrique Barboza Date: Wed, 22 Feb 2023 15:51:58 -0300 Subject: [PATCH 03/10] target/riscv: allow MISA writes as experimental At this moment, and apparently since ever, we have no way of enabling RISCV_FEATURE_MISA. This means that all the code from write_misa(), all the nuts and bolts that handles how to properly write this CSR, has always been a no-op as well because write_misa() will always exit earlier. This seems to be benign in the majority of cases. Booting an Ubuntu 'virt' guest and logging all the calls to 'write_misa' shows that no writes to MISA CSR was attempted. Writing MISA, i.e. enabling/disabling RISC-V extensions after the machine is powered on, seems to be a niche use. After discussions in the mailing list, most notably in [1], we reached the consensus that this code is not suited to be exposed to users because it's not well tested, but at the same time removing it is a bit extreme because we would like to fix it, and it's easier to do so with the code available to use instead of fetching it from git log. The approach taken here is to get rid of RISCV_FEATURE_MISA altogether and use a new experimental flag called x-misa-w. The default value is false, meaning that we're keeping the existing behavior of doing nothing if a write_misa() is attempted. As with any existing experimental flag, x-misa-w is also a temporary flag that we need to remove once we fix write_misa(). [1] https://lists.gnu.org/archive/html/qemu-devel/2023-02/msg05092.html Signed-off-by: Daniel Henrique Barboza Reviewed-by: Weiwei Li Reviewed-by: Andrew Jones Reviewed-by: Bin Meng Reviewed-by: Weiwei Li Reviewed-by: LIU Zhiwei Message-ID: <20230222185205.355361-4-dbarboza@ventanamicro.com> Signed-off-by: Palmer Dabbelt --- target/riscv/cpu.c | 6 ++++++ target/riscv/cpu.h | 2 +- target/riscv/csr.c | 2 +- 3 files changed, 8 insertions(+), 2 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 93b52b826c..1d637b1acd 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -1210,6 +1210,12 @@ static Property riscv_cpu_properties[] = { DEFINE_PROP_BOOL("rvv_ta_all_1s", RISCVCPU, cfg.rvv_ta_all_1s, false), DEFINE_PROP_BOOL("rvv_ma_all_1s", RISCVCPU, cfg.rvv_ma_all_1s, false), + + /* + * write_misa() is marked as experimental for now so mark + * it with -x and default to 'false'. + */ + DEFINE_PROP_BOOL("x-misa-w", RISCVCPU, cfg.misa_w, false), DEFINE_PROP_END_OF_LIST(), }; diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 7ee22cbfa1..ca828424c1 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -89,7 +89,6 @@ enum { RISCV_FEATURE_MMU, RISCV_FEATURE_PMP, RISCV_FEATURE_EPMP, - RISCV_FEATURE_MISA, RISCV_FEATURE_DEBUG }; @@ -498,6 +497,7 @@ struct RISCVCPUConfig { bool pmp; bool epmp; bool debug; + bool misa_w; bool short_isa_string; }; diff --git a/target/riscv/csr.c b/target/riscv/csr.c index e149b453da..3cb8d2ffad 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -1329,7 +1329,7 @@ static RISCVException read_misa(CPURISCVState *env, int csrno, static RISCVException write_misa(CPURISCVState *env, int csrno, target_ulong val) { - if (!riscv_feature(env, RISCV_FEATURE_MISA)) { + if (!riscv_cpu_cfg(env)->misa_w) { /* drop write to misa */ return RISCV_EXCP_NONE; } From cdfb290569fc80e9fb07c86c6de8ae8068fba000 Mon Sep 17 00:00:00 2001 From: Daniel Henrique Barboza Date: Wed, 22 Feb 2023 15:51:59 -0300 Subject: [PATCH 04/10] target/riscv: remove RISCV_FEATURE_DEBUG RISCV_FEATURE_DEBUG will always follow the value defined by cpu->cfg.debug flag. Read the flag instead. Signed-off-by: Daniel Henrique Barboza Reviewed-by: Weiwei Li Reviewed-by: Bin Meng Reviewed-by: Andrew Jones Reviewed-by: LIU Zhiwei Message-ID: <20230222185205.355361-5-dbarboza@ventanamicro.com> Signed-off-by: Palmer Dabbelt --- target/riscv/cpu.c | 6 +----- target/riscv/cpu.h | 1 - target/riscv/cpu_helper.c | 2 +- target/riscv/csr.c | 2 +- target/riscv/machine.c | 3 +-- 5 files changed, 4 insertions(+), 10 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 1d637b1acd..13e55ec5bd 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -637,7 +637,7 @@ static void riscv_cpu_reset_hold(Object *obj) set_default_nan_mode(1, &env->fp_status); #ifndef CONFIG_USER_ONLY - if (riscv_feature(env, RISCV_FEATURE_DEBUG)) { + if (cpu->cfg.debug) { riscv_trigger_init(env); } @@ -935,10 +935,6 @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp) } } - if (cpu->cfg.debug) { - riscv_set_feature(env, RISCV_FEATURE_DEBUG); - } - #ifndef CONFIG_USER_ONLY if (cpu->cfg.ext_sstc) { diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index ca828424c1..dc62554e14 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -89,7 +89,6 @@ enum { RISCV_FEATURE_MMU, RISCV_FEATURE_PMP, RISCV_FEATURE_EPMP, - RISCV_FEATURE_DEBUG }; /* Privileged specification version */ diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index 3a9472a2ff..7ae832e829 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -105,7 +105,7 @@ void cpu_get_tb_cpu_state(CPURISCVState *env, target_ulong *pc, flags = FIELD_DP32(flags, TB_FLAGS, MSTATUS_HS_VS, get_field(env->mstatus_hs, MSTATUS_VS)); } - if (riscv_feature(env, RISCV_FEATURE_DEBUG) && !icount_enabled()) { + if (cpu->cfg.debug && !icount_enabled()) { flags = FIELD_DP32(flags, TB_FLAGS, ITRIGGER, env->itrigger_enabled); } #endif diff --git a/target/riscv/csr.c b/target/riscv/csr.c index 3cb8d2ffad..e220c4a5fd 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -437,7 +437,7 @@ static RISCVException epmp(CPURISCVState *env, int csrno) static RISCVException debug(CPURISCVState *env, int csrno) { - if (riscv_feature(env, RISCV_FEATURE_DEBUG)) { + if (riscv_cpu_cfg(env)->debug) { return RISCV_EXCP_NONE; } diff --git a/target/riscv/machine.c b/target/riscv/machine.c index c6ce318cce..4634968898 100644 --- a/target/riscv/machine.c +++ b/target/riscv/machine.c @@ -226,9 +226,8 @@ static const VMStateDescription vmstate_kvmtimer = { static bool debug_needed(void *opaque) { RISCVCPU *cpu = opaque; - CPURISCVState *env = &cpu->env; - return riscv_feature(env, RISCV_FEATURE_DEBUG); + return cpu->cfg.debug; } static int debug_post_load(void *opaque, int version_id) From 09631441e5bdd164f737d4e10a4a0e3dcc1c90a7 Mon Sep 17 00:00:00 2001 From: Daniel Henrique Barboza Date: Wed, 22 Feb 2023 15:52:00 -0300 Subject: [PATCH 05/10] target/riscv/cpu.c: error out if EPMP is enabled without PMP Instead of silently ignoring the EPMP setting if there is no PMP available, error out informing the user that EPMP depends on PMP support: $ ./qemu-system-riscv64 -cpu rv64,pmp=false,x-epmp=true qemu-system-riscv64: Invalid configuration: EPMP requires PMP support This will force users to pick saner options in the QEMU command line. Signed-off-by: Daniel Henrique Barboza Reviewed-by: Weiwei Li Reviewed-by: Bin Meng Reviewed-by: Andrew Jones Reviewed-by: LIU Zhiwei Message-ID: <20230222185205.355361-6-dbarboza@ventanamicro.com> Signed-off-by: Palmer Dabbelt --- target/riscv/cpu.c | 9 +++++++-- 1 file changed, 7 insertions(+), 2 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 13e55ec5bd..aec7830c44 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -925,13 +925,18 @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp) if (cpu->cfg.pmp) { riscv_set_feature(env, RISCV_FEATURE_PMP); + } + + if (cpu->cfg.epmp) { + riscv_set_feature(env, RISCV_FEATURE_EPMP); /* * Enhanced PMP should only be available * on harts with PMP support */ - if (cpu->cfg.epmp) { - riscv_set_feature(env, RISCV_FEATURE_EPMP); + if (!cpu->cfg.pmp) { + error_setg(errp, "Invalid configuration: EPMP requires PMP support"); + return; } } From 6a3ffda2ba4f3d4895c8d45d35feb61ddbd3a4f5 Mon Sep 17 00:00:00 2001 From: Daniel Henrique Barboza Date: Wed, 22 Feb 2023 15:52:01 -0300 Subject: [PATCH 06/10] target/riscv: remove RISCV_FEATURE_EPMP RISCV_FEATURE_EPMP is always set to the same value as the cpu->cfg.epmp flag. Use the flag directly. Signed-off-by: Daniel Henrique Barboza Reviewed-by: Weiwei Li Reviewed-by: Bin Meng Reviewed-by: Andrew Jones Reviewed-by: LIU Zhiwei Message-ID: <20230222185205.355361-7-dbarboza@ventanamicro.com> Signed-off-by: Palmer Dabbelt --- target/riscv/cpu.c | 10 +++------- target/riscv/cpu.h | 1 - target/riscv/csr.c | 2 +- target/riscv/pmp.c | 4 ++-- 4 files changed, 6 insertions(+), 11 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index aec7830c44..807a466f34 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -927,17 +927,13 @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp) riscv_set_feature(env, RISCV_FEATURE_PMP); } - if (cpu->cfg.epmp) { - riscv_set_feature(env, RISCV_FEATURE_EPMP); - + if (cpu->cfg.epmp && !cpu->cfg.pmp) { /* * Enhanced PMP should only be available * on harts with PMP support */ - if (!cpu->cfg.pmp) { - error_setg(errp, "Invalid configuration: EPMP requires PMP support"); - return; - } + error_setg(errp, "Invalid configuration: EPMP requires PMP support"); + return; } diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index dc62554e14..471e587729 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -88,7 +88,6 @@ enum { RISCV_FEATURE_MMU, RISCV_FEATURE_PMP, - RISCV_FEATURE_EPMP, }; /* Privileged specification version */ diff --git a/target/riscv/csr.c b/target/riscv/csr.c index e220c4a5fd..951327022d 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -428,7 +428,7 @@ static RISCVException pmp(CPURISCVState *env, int csrno) static RISCVException epmp(CPURISCVState *env, int csrno) { - if (env->priv == PRV_M && riscv_feature(env, RISCV_FEATURE_EPMP)) { + if (env->priv == PRV_M && riscv_cpu_cfg(env)->epmp) { return RISCV_EXCP_NONE; } diff --git a/target/riscv/pmp.c b/target/riscv/pmp.c index 4bc4113531..aa4d1996e9 100644 --- a/target/riscv/pmp.c +++ b/target/riscv/pmp.c @@ -88,7 +88,7 @@ static void pmp_write_cfg(CPURISCVState *env, uint32_t pmp_index, uint8_t val) if (pmp_index < MAX_RISCV_PMPS) { bool locked = true; - if (riscv_feature(env, RISCV_FEATURE_EPMP)) { + if (riscv_cpu_cfg(env)->epmp) { /* mseccfg.RLB is set */ if (MSECCFG_RLB_ISSET(env)) { locked = false; @@ -239,7 +239,7 @@ static bool pmp_hart_has_privs_default(CPURISCVState *env, target_ulong addr, { bool ret; - if (riscv_feature(env, RISCV_FEATURE_EPMP)) { + if (riscv_cpu_cfg(env)->epmp) { if (MSECCFG_MMWP_ISSET(env)) { /* * The Machine Mode Whitelist Policy (mseccfg.MMWP) is set From 3fe40ef5a90d62e5695c18ec8aa517a0694ce7ed Mon Sep 17 00:00:00 2001 From: Daniel Henrique Barboza Date: Wed, 22 Feb 2023 15:52:02 -0300 Subject: [PATCH 07/10] target/riscv: remove RISCV_FEATURE_PMP RISCV_FEATURE_PMP is being set via riscv_set_feature() by mirroring the cpu->cfg.pmp flag. Use the flag instead. Signed-off-by: Daniel Henrique Barboza Reviewed-by: Weiwei Li Reviewed-by: Bin Meng Reviewed-by: Andrew Jones Reviewed-by: LIU Zhiwei Message-ID: <20230222185205.355361-8-dbarboza@ventanamicro.com> Signed-off-by: Palmer Dabbelt --- target/riscv/cpu.c | 4 ---- target/riscv/cpu.h | 1 - target/riscv/cpu_helper.c | 2 +- target/riscv/csr.c | 2 +- target/riscv/machine.c | 3 +-- target/riscv/op_helper.c | 2 +- target/riscv/pmp.c | 2 +- 7 files changed, 5 insertions(+), 11 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 807a466f34..d321ad28d2 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -923,10 +923,6 @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp) riscv_set_feature(env, RISCV_FEATURE_MMU); } - if (cpu->cfg.pmp) { - riscv_set_feature(env, RISCV_FEATURE_PMP); - } - if (cpu->cfg.epmp && !cpu->cfg.pmp) { /* * Enhanced PMP should only be available diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 471e587729..d3f9f29f4c 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -87,7 +87,6 @@ so a cpu features bitfield is required, likewise for optional PMP support */ enum { RISCV_FEATURE_MMU, - RISCV_FEATURE_PMP, }; /* Privileged specification version */ diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index 7ae832e829..57d20c605b 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -706,7 +706,7 @@ static int get_physical_address_pmp(CPURISCVState *env, int *prot, pmp_priv_t pmp_priv; int pmp_index = -1; - if (!riscv_feature(env, RISCV_FEATURE_PMP)) { + if (!riscv_cpu_cfg(env)->pmp) { *prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC; return TRANSLATE_SUCCESS; } diff --git a/target/riscv/csr.c b/target/riscv/csr.c index 951327022d..cf33494945 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -419,7 +419,7 @@ static int aia_hmode32(CPURISCVState *env, int csrno) static RISCVException pmp(CPURISCVState *env, int csrno) { - if (riscv_feature(env, RISCV_FEATURE_PMP)) { + if (riscv_cpu_cfg(env)->pmp) { return RISCV_EXCP_NONE; } diff --git a/target/riscv/machine.c b/target/riscv/machine.c index 4634968898..67e9e56853 100644 --- a/target/riscv/machine.c +++ b/target/riscv/machine.c @@ -27,9 +27,8 @@ static bool pmp_needed(void *opaque) { RISCVCPU *cpu = opaque; - CPURISCVState *env = &cpu->env; - return riscv_feature(env, RISCV_FEATURE_PMP); + return cpu->cfg.pmp; } static int pmp_post_load(void *opaque, int version_id) diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c index 48f918b71b..9c0b91c88f 100644 --- a/target/riscv/op_helper.c +++ b/target/riscv/op_helper.c @@ -195,7 +195,7 @@ target_ulong helper_mret(CPURISCVState *env) uint64_t mstatus = env->mstatus; target_ulong prev_priv = get_field(mstatus, MSTATUS_MPP); - if (riscv_feature(env, RISCV_FEATURE_PMP) && + if (riscv_cpu_cfg(env)->pmp && !pmp_get_num_rules(env) && (prev_priv != PRV_M)) { riscv_raise_exception(env, RISCV_EXCP_INST_ACCESS_FAULT, GETPC()); } diff --git a/target/riscv/pmp.c b/target/riscv/pmp.c index aa4d1996e9..205bfbe090 100644 --- a/target/riscv/pmp.c +++ b/target/riscv/pmp.c @@ -265,7 +265,7 @@ static bool pmp_hart_has_privs_default(CPURISCVState *env, target_ulong addr, } } - if ((!riscv_feature(env, RISCV_FEATURE_PMP)) || (mode == PRV_M)) { + if (!riscv_cpu_cfg(env)->pmp || (mode == PRV_M)) { /* * Privileged spec v1.10 states if HW doesn't implement any PMP entry * or no PMP entry matches an M-Mode access, the access succeeds. From c95c9d200e22b17858ec9287b6a9716d053e48aa Mon Sep 17 00:00:00 2001 From: Daniel Henrique Barboza Date: Wed, 22 Feb 2023 15:52:03 -0300 Subject: [PATCH 08/10] hw/riscv/virt.c: do not use RISCV_FEATURE_MMU in create_fdt_socket_cpus() Read cpu_ptr->cfg.mmu directly. As a bonus, use cpu_ptr in riscv_isa_string(). Signed-off-by: Daniel Henrique Barboza Reviewed-by: Weiwei Li Reviewed-by: Bin Meng Reviewed-by: Andrew Jones Reviewed-by: LIU Zhiwei Message-ID: <20230222185205.355361-9-dbarboza@ventanamicro.com> Signed-off-by: Palmer Dabbelt --- hw/riscv/virt.c | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c index 86c4adc0c9..49f2c157f7 100644 --- a/hw/riscv/virt.c +++ b/hw/riscv/virt.c @@ -232,20 +232,21 @@ static void create_fdt_socket_cpus(RISCVVirtState *s, int socket, bool is_32_bit = riscv_is_32bit(&s->soc[0]); for (cpu = s->soc[socket].num_harts - 1; cpu >= 0; cpu--) { + RISCVCPU *cpu_ptr = &s->soc[socket].harts[cpu]; + cpu_phandle = (*phandle)++; cpu_name = g_strdup_printf("/cpus/cpu@%d", s->soc[socket].hartid_base + cpu); qemu_fdt_add_subnode(ms->fdt, cpu_name); - if (riscv_feature(&s->soc[socket].harts[cpu].env, - RISCV_FEATURE_MMU)) { + if (cpu_ptr->cfg.mmu) { qemu_fdt_setprop_string(ms->fdt, cpu_name, "mmu-type", (is_32_bit) ? "riscv,sv32" : "riscv,sv48"); } else { qemu_fdt_setprop_string(ms->fdt, cpu_name, "mmu-type", "riscv,none"); } - name = riscv_isa_string(&s->soc[socket].harts[cpu]); + name = riscv_isa_string(cpu_ptr); qemu_fdt_setprop_string(ms->fdt, cpu_name, "riscv,isa", name); g_free(name); qemu_fdt_setprop_string(ms->fdt, cpu_name, "compatible", "riscv"); From dcf654a3e899ac2569393ca3a4747c3776d9c9a3 Mon Sep 17 00:00:00 2001 From: Daniel Henrique Barboza Date: Wed, 22 Feb 2023 15:52:04 -0300 Subject: [PATCH 09/10] target/riscv: remove RISCV_FEATURE_MMU RISCV_FEATURE_MMU is set whether cpu->cfg.mmu is set, so let's just use the flag directly instead. With this change the enum is also removed. It is worth noticing that this enum, and all the RISCV_FEATURES_* that were contained in it, predates the existence of the cpu->cfg object. Today, using cpu->cfg is an easier way to retrieve all the features and extensions enabled in the hart. Signed-off-by: Daniel Henrique Barboza Reviewed-by: Weiwei Li Reviewed-by: Bin Meng Reviewed-by: Andrew Jones Reviewed-by: LIU Zhiwei Message-ID: <20230222185205.355361-10-dbarboza@ventanamicro.com> Signed-off-by: Palmer Dabbelt --- target/riscv/cpu.c | 4 ---- target/riscv/cpu.h | 7 ------- target/riscv/cpu_helper.c | 2 +- target/riscv/csr.c | 4 ++-- target/riscv/monitor.c | 2 +- target/riscv/pmp.c | 2 +- 6 files changed, 5 insertions(+), 16 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index d321ad28d2..11da920915 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -919,10 +919,6 @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp) } } - if (cpu->cfg.mmu) { - riscv_set_feature(env, RISCV_FEATURE_MMU); - } - if (cpu->cfg.epmp && !cpu->cfg.pmp) { /* * Enhanced PMP should only be available diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index d3f9f29f4c..ac33362525 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -81,13 +81,6 @@ #define RVH RV('H') #define RVJ RV('J') -/* S extension denotes that Supervisor mode exists, however it is possible - to have a core that support S mode but does not have an MMU and there - is currently no bit in misa to indicate whether an MMU exists or not - so a cpu features bitfield is required, likewise for optional PMP support */ -enum { - RISCV_FEATURE_MMU, -}; /* Privileged specification version */ enum { diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index 57d20c605b..2b731a8c7f 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -796,7 +796,7 @@ static int get_physical_address(CPURISCVState *env, hwaddr *physical, mode = PRV_U; } - if (mode == PRV_M || !riscv_feature(env, RISCV_FEATURE_MMU)) { + if (mode == PRV_M || !riscv_cpu_cfg(env)->mmu) { *physical = addr; *prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC; return TRANSLATE_SUCCESS; diff --git a/target/riscv/csr.c b/target/riscv/csr.c index cf33494945..75a540bfcb 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -2621,7 +2621,7 @@ static RISCVException rmw_siph(CPURISCVState *env, int csrno, static RISCVException read_satp(CPURISCVState *env, int csrno, target_ulong *val) { - if (!riscv_feature(env, RISCV_FEATURE_MMU)) { + if (!riscv_cpu_cfg(env)->mmu) { *val = 0; return RISCV_EXCP_NONE; } @@ -2640,7 +2640,7 @@ static RISCVException write_satp(CPURISCVState *env, int csrno, { target_ulong vm, mask; - if (!riscv_feature(env, RISCV_FEATURE_MMU)) { + if (!riscv_cpu_cfg(env)->mmu) { return RISCV_EXCP_NONE; } diff --git a/target/riscv/monitor.c b/target/riscv/monitor.c index 236f93b9f5..f36ddfa967 100644 --- a/target/riscv/monitor.c +++ b/target/riscv/monitor.c @@ -218,7 +218,7 @@ void hmp_info_mem(Monitor *mon, const QDict *qdict) return; } - if (!riscv_feature(env, RISCV_FEATURE_MMU)) { + if (!riscv_cpu_cfg(env)->mmu) { monitor_printf(mon, "S-mode MMU unavailable\n"); return; } diff --git a/target/riscv/pmp.c b/target/riscv/pmp.c index 205bfbe090..a08cd95658 100644 --- a/target/riscv/pmp.c +++ b/target/riscv/pmp.c @@ -315,7 +315,7 @@ int pmp_hart_has_privs(CPURISCVState *env, target_ulong addr, } if (size == 0) { - if (riscv_feature(env, RISCV_FEATURE_MMU)) { + if (riscv_cpu_cfg(env)->mmu) { /* * If size is unknown (0), assume that all bytes * from addr to the end of the page will be accessed. From 1e2de2b8280a518a6178e7d4dda6c9906d8a86f2 Mon Sep 17 00:00:00 2001 From: Daniel Henrique Barboza Date: Wed, 22 Feb 2023 15:52:05 -0300 Subject: [PATCH 10/10] target/riscv/cpu: remove CPUArchState::features and friends The attribute is no longer used since we can retrieve all the enabled features in the hart by using cpu->cfg instead. Remove env->feature, riscv_feature() and riscv_set_feature(). We also need to bump vmstate_riscv_cpu version_id and minimal_version_id since 'features' is no longer being migrated. Signed-off-by: Daniel Henrique Barboza Reviewed-by: Weiwei Li Reviewed-by: Bin Meng Reviewed-by: Andrew Jones Reviewed-by: LIU Zhiwei Message-ID: <20230222185205.355361-11-dbarboza@ventanamicro.com> Signed-off-by: Palmer Dabbelt --- target/riscv/cpu.h | 12 ------------ target/riscv/machine.c | 5 ++--- 2 files changed, 2 insertions(+), 15 deletions(-) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index ac33362525..b9f69a134b 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -175,8 +175,6 @@ struct CPUArchState { /* 128-bit helpers upper part return value */ target_ulong retxh; - uint32_t features; - #ifdef CONFIG_USER_ONLY uint32_t elf_flags; #endif @@ -525,16 +523,6 @@ static inline int riscv_has_ext(CPURISCVState *env, target_ulong ext) return (env->misa_ext & ext) != 0; } -static inline bool riscv_feature(CPURISCVState *env, int feature) -{ - return env->features & (1ULL << feature); -} - -static inline void riscv_set_feature(CPURISCVState *env, int feature) -{ - env->features |= (1ULL << feature); -} - #include "cpu_user.h" extern const char * const riscv_int_regnames[]; diff --git a/target/riscv/machine.c b/target/riscv/machine.c index 67e9e56853..9c455931d8 100644 --- a/target/riscv/machine.c +++ b/target/riscv/machine.c @@ -331,8 +331,8 @@ static const VMStateDescription vmstate_pmu_ctr_state = { const VMStateDescription vmstate_riscv_cpu = { .name = "cpu", - .version_id = 6, - .minimum_version_id = 6, + .version_id = 7, + .minimum_version_id = 7, .post_load = riscv_cpu_post_load, .fields = (VMStateField[]) { VMSTATE_UINTTL_ARRAY(env.gpr, RISCVCPU, 32), @@ -351,7 +351,6 @@ const VMStateDescription vmstate_riscv_cpu = { VMSTATE_UINT32(env.misa_ext, RISCVCPU), VMSTATE_UINT32(env.misa_mxl_max, RISCVCPU), VMSTATE_UINT32(env.misa_ext_mask, RISCVCPU), - VMSTATE_UINT32(env.features, RISCVCPU), VMSTATE_UINTTL(env.priv, RISCVCPU), VMSTATE_UINTTL(env.virt, RISCVCPU), VMSTATE_UINT64(env.resetvec, RISCVCPU),