target/arm: Convert Neon VTRN to decodetree
Convert the Neon VTRN insn to decodetree. This is the last insn in the Neon data-processing group, so we can remove all the now-unused old decoder framework. It's possible that there's a more efficient implementation of VTRN, but for this conversion we just copy the existing approach. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20200616170844.13318-21-peter.maydell@linaro.org
This commit is contained in:
Peter Maydell
parent
8ab3a227a0
commit
d4366190f8
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@ -489,7 +489,7 @@ Vimm_1r 1111 001 . 1 . 000 ... .... cmode:4 0 . op:1 1 .... @1reg_imm
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VNEG_F 1111 001 11 . 11 .. 01 .... 0 1111 . . 0 .... @2misc
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VSWP 1111 001 11 . 11 .. 10 .... 0 0000 . . 0 .... @2misc
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VTRN 1111 001 11 . 11 .. 10 .... 0 0001 . . 0 .... @2misc
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VUZP 1111 001 11 . 11 .. 10 .... 0 0010 . . 0 .... @2misc
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VZIP 1111 001 11 . 11 .. 10 .... 0 0011 . . 0 .... @2misc
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@ -3968,3 +3968,93 @@ static bool trans_VSWP(DisasContext *s, arg_2misc *a)
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return true;
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}
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static void gen_neon_trn_u8(TCGv_i32 t0, TCGv_i32 t1)
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{
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TCGv_i32 rd, tmp;
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rd = tcg_temp_new_i32();
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tmp = tcg_temp_new_i32();
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tcg_gen_shli_i32(rd, t0, 8);
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tcg_gen_andi_i32(rd, rd, 0xff00ff00);
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tcg_gen_andi_i32(tmp, t1, 0x00ff00ff);
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tcg_gen_or_i32(rd, rd, tmp);
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tcg_gen_shri_i32(t1, t1, 8);
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tcg_gen_andi_i32(t1, t1, 0x00ff00ff);
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tcg_gen_andi_i32(tmp, t0, 0xff00ff00);
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tcg_gen_or_i32(t1, t1, tmp);
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tcg_gen_mov_i32(t0, rd);
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tcg_temp_free_i32(tmp);
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tcg_temp_free_i32(rd);
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}
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static void gen_neon_trn_u16(TCGv_i32 t0, TCGv_i32 t1)
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{
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TCGv_i32 rd, tmp;
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rd = tcg_temp_new_i32();
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tmp = tcg_temp_new_i32();
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tcg_gen_shli_i32(rd, t0, 16);
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tcg_gen_andi_i32(tmp, t1, 0xffff);
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tcg_gen_or_i32(rd, rd, tmp);
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tcg_gen_shri_i32(t1, t1, 16);
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tcg_gen_andi_i32(tmp, t0, 0xffff0000);
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tcg_gen_or_i32(t1, t1, tmp);
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tcg_gen_mov_i32(t0, rd);
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tcg_temp_free_i32(tmp);
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tcg_temp_free_i32(rd);
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}
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static bool trans_VTRN(DisasContext *s, arg_2misc *a)
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{
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TCGv_i32 tmp, tmp2;
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int pass;
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if (!arm_dc_feature(s, ARM_FEATURE_NEON)) {
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return false;
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}
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/* UNDEF accesses to D16-D31 if they don't exist. */
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if (!dc_isar_feature(aa32_simd_r32, s) &&
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((a->vd | a->vm) & 0x10)) {
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return false;
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}
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if ((a->vd | a->vm) & a->q) {
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return false;
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}
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if (a->size == 3) {
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return false;
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}
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if (!vfp_access_check(s)) {
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return true;
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}
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if (a->size == 2) {
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for (pass = 0; pass < (a->q ? 4 : 2); pass += 2) {
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tmp = neon_load_reg(a->vm, pass);
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tmp2 = neon_load_reg(a->vd, pass + 1);
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neon_store_reg(a->vm, pass, tmp2);
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neon_store_reg(a->vd, pass + 1, tmp);
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}
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} else {
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for (pass = 0; pass < (a->q ? 4 : 2); pass++) {
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tmp = neon_load_reg(a->vm, pass);
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tmp2 = neon_load_reg(a->vd, pass);
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if (a->size == 0) {
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gen_neon_trn_u8(tmp, tmp2);
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} else {
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gen_neon_trn_u16(tmp, tmp2);
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}
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neon_store_reg(a->vm, pass, tmp2);
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neon_store_reg(a->vd, pass, tmp);
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}
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}
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return true;
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}
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@ -2934,183 +2934,6 @@ static void gen_exception_return(DisasContext *s, TCGv_i32 pc)
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gen_rfe(s, pc, load_cpu_field(spsr));
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}
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static void gen_neon_trn_u8(TCGv_i32 t0, TCGv_i32 t1)
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{
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TCGv_i32 rd, tmp;
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rd = tcg_temp_new_i32();
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tmp = tcg_temp_new_i32();
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tcg_gen_shli_i32(rd, t0, 8);
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tcg_gen_andi_i32(rd, rd, 0xff00ff00);
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tcg_gen_andi_i32(tmp, t1, 0x00ff00ff);
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tcg_gen_or_i32(rd, rd, tmp);
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tcg_gen_shri_i32(t1, t1, 8);
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tcg_gen_andi_i32(t1, t1, 0x00ff00ff);
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tcg_gen_andi_i32(tmp, t0, 0xff00ff00);
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tcg_gen_or_i32(t1, t1, tmp);
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tcg_gen_mov_i32(t0, rd);
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tcg_temp_free_i32(tmp);
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tcg_temp_free_i32(rd);
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}
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static void gen_neon_trn_u16(TCGv_i32 t0, TCGv_i32 t1)
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{
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TCGv_i32 rd, tmp;
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rd = tcg_temp_new_i32();
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tmp = tcg_temp_new_i32();
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tcg_gen_shli_i32(rd, t0, 16);
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tcg_gen_andi_i32(tmp, t1, 0xffff);
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tcg_gen_or_i32(rd, rd, tmp);
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tcg_gen_shri_i32(t1, t1, 16);
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tcg_gen_andi_i32(tmp, t0, 0xffff0000);
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tcg_gen_or_i32(t1, t1, tmp);
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tcg_gen_mov_i32(t0, rd);
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tcg_temp_free_i32(tmp);
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tcg_temp_free_i32(rd);
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}
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/* Symbolic constants for op fields for Neon 2-register miscellaneous.
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* The values correspond to bits [17:16,10:7]; see the ARM ARM DDI0406B
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* table A7-13.
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*/
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#define NEON_2RM_VREV64 0
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#define NEON_2RM_VREV32 1
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#define NEON_2RM_VREV16 2
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#define NEON_2RM_VPADDL 4
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#define NEON_2RM_VPADDL_U 5
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#define NEON_2RM_AESE 6 /* Includes AESD */
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#define NEON_2RM_AESMC 7 /* Includes AESIMC */
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#define NEON_2RM_VCLS 8
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#define NEON_2RM_VCLZ 9
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#define NEON_2RM_VCNT 10
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#define NEON_2RM_VMVN 11
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#define NEON_2RM_VPADAL 12
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#define NEON_2RM_VPADAL_U 13
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#define NEON_2RM_VQABS 14
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#define NEON_2RM_VQNEG 15
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#define NEON_2RM_VCGT0 16
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#define NEON_2RM_VCGE0 17
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#define NEON_2RM_VCEQ0 18
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#define NEON_2RM_VCLE0 19
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#define NEON_2RM_VCLT0 20
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#define NEON_2RM_SHA1H 21
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#define NEON_2RM_VABS 22
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#define NEON_2RM_VNEG 23
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#define NEON_2RM_VCGT0_F 24
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#define NEON_2RM_VCGE0_F 25
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#define NEON_2RM_VCEQ0_F 26
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#define NEON_2RM_VCLE0_F 27
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#define NEON_2RM_VCLT0_F 28
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#define NEON_2RM_VABS_F 30
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#define NEON_2RM_VNEG_F 31
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#define NEON_2RM_VSWP 32
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#define NEON_2RM_VTRN 33
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#define NEON_2RM_VUZP 34
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#define NEON_2RM_VZIP 35
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#define NEON_2RM_VMOVN 36 /* Includes VQMOVN, VQMOVUN */
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#define NEON_2RM_VQMOVN 37 /* Includes VQMOVUN */
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#define NEON_2RM_VSHLL 38
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#define NEON_2RM_SHA1SU1 39 /* Includes SHA256SU0 */
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#define NEON_2RM_VRINTN 40
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#define NEON_2RM_VRINTX 41
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#define NEON_2RM_VRINTA 42
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#define NEON_2RM_VRINTZ 43
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#define NEON_2RM_VCVT_F16_F32 44
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#define NEON_2RM_VRINTM 45
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#define NEON_2RM_VCVT_F32_F16 46
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#define NEON_2RM_VRINTP 47
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#define NEON_2RM_VCVTAU 48
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#define NEON_2RM_VCVTAS 49
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#define NEON_2RM_VCVTNU 50
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#define NEON_2RM_VCVTNS 51
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#define NEON_2RM_VCVTPU 52
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#define NEON_2RM_VCVTPS 53
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#define NEON_2RM_VCVTMU 54
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#define NEON_2RM_VCVTMS 55
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#define NEON_2RM_VRECPE 56
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#define NEON_2RM_VRSQRTE 57
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#define NEON_2RM_VRECPE_F 58
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#define NEON_2RM_VRSQRTE_F 59
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#define NEON_2RM_VCVT_FS 60
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#define NEON_2RM_VCVT_FU 61
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#define NEON_2RM_VCVT_SF 62
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#define NEON_2RM_VCVT_UF 63
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/* Each entry in this array has bit n set if the insn allows
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* size value n (otherwise it will UNDEF). Since unallocated
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* op values will have no bits set they always UNDEF.
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*/
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static const uint8_t neon_2rm_sizes[] = {
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[NEON_2RM_VREV64] = 0x7,
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[NEON_2RM_VREV32] = 0x3,
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[NEON_2RM_VREV16] = 0x1,
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[NEON_2RM_VPADDL] = 0x7,
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[NEON_2RM_VPADDL_U] = 0x7,
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[NEON_2RM_AESE] = 0x1,
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[NEON_2RM_AESMC] = 0x1,
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[NEON_2RM_VCLS] = 0x7,
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[NEON_2RM_VCLZ] = 0x7,
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[NEON_2RM_VCNT] = 0x1,
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[NEON_2RM_VMVN] = 0x1,
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[NEON_2RM_VPADAL] = 0x7,
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[NEON_2RM_VPADAL_U] = 0x7,
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[NEON_2RM_VQABS] = 0x7,
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[NEON_2RM_VQNEG] = 0x7,
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[NEON_2RM_VCGT0] = 0x7,
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[NEON_2RM_VCGE0] = 0x7,
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[NEON_2RM_VCEQ0] = 0x7,
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[NEON_2RM_VCLE0] = 0x7,
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[NEON_2RM_VCLT0] = 0x7,
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[NEON_2RM_SHA1H] = 0x4,
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[NEON_2RM_VABS] = 0x7,
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[NEON_2RM_VNEG] = 0x7,
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[NEON_2RM_VCGT0_F] = 0x4,
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[NEON_2RM_VCGE0_F] = 0x4,
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[NEON_2RM_VCEQ0_F] = 0x4,
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[NEON_2RM_VCLE0_F] = 0x4,
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[NEON_2RM_VCLT0_F] = 0x4,
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[NEON_2RM_VABS_F] = 0x4,
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[NEON_2RM_VNEG_F] = 0x4,
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[NEON_2RM_VSWP] = 0x1,
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[NEON_2RM_VTRN] = 0x7,
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[NEON_2RM_VUZP] = 0x7,
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[NEON_2RM_VZIP] = 0x7,
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[NEON_2RM_VMOVN] = 0x7,
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[NEON_2RM_VQMOVN] = 0x7,
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[NEON_2RM_VSHLL] = 0x7,
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[NEON_2RM_SHA1SU1] = 0x4,
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[NEON_2RM_VRINTN] = 0x4,
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[NEON_2RM_VRINTX] = 0x4,
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[NEON_2RM_VRINTA] = 0x4,
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[NEON_2RM_VRINTZ] = 0x4,
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[NEON_2RM_VCVT_F16_F32] = 0x2,
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[NEON_2RM_VRINTM] = 0x4,
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[NEON_2RM_VCVT_F32_F16] = 0x2,
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[NEON_2RM_VRINTP] = 0x4,
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[NEON_2RM_VCVTAU] = 0x4,
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[NEON_2RM_VCVTAS] = 0x4,
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[NEON_2RM_VCVTNU] = 0x4,
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[NEON_2RM_VCVTNS] = 0x4,
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[NEON_2RM_VCVTPU] = 0x4,
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[NEON_2RM_VCVTPS] = 0x4,
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[NEON_2RM_VCVTMU] = 0x4,
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[NEON_2RM_VCVTMS] = 0x4,
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[NEON_2RM_VRECPE] = 0x4,
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[NEON_2RM_VRSQRTE] = 0x4,
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[NEON_2RM_VRECPE_F] = 0x4,
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[NEON_2RM_VRSQRTE_F] = 0x4,
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[NEON_2RM_VCVT_FS] = 0x4,
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[NEON_2RM_VCVT_FU] = 0x4,
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[NEON_2RM_VCVT_SF] = 0x4,
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[NEON_2RM_VCVT_UF] = 0x4,
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};
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static void gen_gvec_fn3_qc(uint32_t rd_ofs, uint32_t rn_ofs, uint32_t rm_ofs,
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uint32_t opr_sz, uint32_t max_sz,
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gen_helper_gvec_3_ptr *fn)
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@ -4822,178 +4645,6 @@ void gen_gvec_uaba(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs,
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tcg_gen_gvec_3(rd_ofs, rn_ofs, rm_ofs, opr_sz, max_sz, &ops[vece]);
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}
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/* Translate a NEON data processing instruction. Return nonzero if the
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instruction is invalid.
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We process data in a mixture of 32-bit and 64-bit chunks.
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Mostly we use 32-bit chunks so we can use normal scalar instructions. */
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static int disas_neon_data_insn(DisasContext *s, uint32_t insn)
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{
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int op;
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int q;
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int rd, rm;
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int size;
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int pass;
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int u;
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TCGv_i32 tmp, tmp2;
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if (!arm_dc_feature(s, ARM_FEATURE_NEON)) {
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return 1;
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}
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/* FIXME: this access check should not take precedence over UNDEF
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* for invalid encodings; we will generate incorrect syndrome information
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* for attempts to execute invalid vfp/neon encodings with FP disabled.
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*/
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if (s->fp_excp_el) {
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gen_exception_insn(s, s->pc_curr, EXCP_UDEF,
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syn_simd_access_trap(1, 0xe, false), s->fp_excp_el);
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return 0;
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}
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if (!s->vfp_enabled)
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return 1;
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q = (insn & (1 << 6)) != 0;
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u = (insn >> 24) & 1;
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VFP_DREG_D(rd, insn);
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VFP_DREG_M(rm, insn);
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size = (insn >> 20) & 3;
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if ((insn & (1 << 23)) == 0) {
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/* Three register same length: handled by decodetree */
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return 1;
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} else if (insn & (1 << 4)) {
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/* Two registers and shift or reg and imm: handled by decodetree */
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return 1;
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} else { /* (insn & 0x00800010 == 0x00800000) */
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if (size != 3) {
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/*
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* Three registers of different lengths, or two registers and
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* a scalar: handled by decodetree
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*/
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return 1;
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} else { /* size == 3 */
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if (!u) {
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/* Extract: handled by decodetree */
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return 1;
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} else if ((insn & (1 << 11)) == 0) {
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/* Two register misc. */
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op = ((insn >> 12) & 0x30) | ((insn >> 7) & 0xf);
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size = (insn >> 18) & 3;
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/* UNDEF for unknown op values and bad op-size combinations */
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if ((neon_2rm_sizes[op] & (1 << size)) == 0) {
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return 1;
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}
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if (q && ((rm | rd) & 1)) {
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return 1;
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}
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switch (op) {
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case NEON_2RM_VREV64:
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case NEON_2RM_VPADDL: case NEON_2RM_VPADDL_U:
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case NEON_2RM_VPADAL: case NEON_2RM_VPADAL_U:
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case NEON_2RM_VUZP:
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case NEON_2RM_VZIP:
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case NEON_2RM_VMOVN: case NEON_2RM_VQMOVN:
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case NEON_2RM_VSHLL:
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case NEON_2RM_VCVT_F16_F32:
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case NEON_2RM_VCVT_F32_F16:
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case NEON_2RM_VMVN:
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case NEON_2RM_VNEG:
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case NEON_2RM_VABS:
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case NEON_2RM_VCEQ0:
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case NEON_2RM_VCGT0:
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case NEON_2RM_VCLE0:
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case NEON_2RM_VCGE0:
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case NEON_2RM_VCLT0:
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case NEON_2RM_AESE: case NEON_2RM_AESMC:
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case NEON_2RM_SHA1H:
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case NEON_2RM_SHA1SU1:
|
||||
case NEON_2RM_VREV32:
|
||||
case NEON_2RM_VREV16:
|
||||
case NEON_2RM_VCLS:
|
||||
case NEON_2RM_VCLZ:
|
||||
case NEON_2RM_VCNT:
|
||||
case NEON_2RM_VABS_F:
|
||||
case NEON_2RM_VNEG_F:
|
||||
case NEON_2RM_VRECPE:
|
||||
case NEON_2RM_VRSQRTE:
|
||||
case NEON_2RM_VQABS:
|
||||
case NEON_2RM_VQNEG:
|
||||
case NEON_2RM_VRECPE_F:
|
||||
case NEON_2RM_VRSQRTE_F:
|
||||
case NEON_2RM_VCVT_FS:
|
||||
case NEON_2RM_VCVT_FU:
|
||||
case NEON_2RM_VCVT_SF:
|
||||
case NEON_2RM_VCVT_UF:
|
||||
case NEON_2RM_VRINTX:
|
||||
case NEON_2RM_VCGT0_F:
|
||||
case NEON_2RM_VCGE0_F:
|
||||
case NEON_2RM_VCEQ0_F:
|
||||
case NEON_2RM_VCLE0_F:
|
||||
case NEON_2RM_VCLT0_F:
|
||||
case NEON_2RM_VRINTN:
|
||||
case NEON_2RM_VRINTA:
|
||||
case NEON_2RM_VRINTM:
|
||||
case NEON_2RM_VRINTP:
|
||||
case NEON_2RM_VRINTZ:
|
||||
case NEON_2RM_VCVTAU:
|
||||
case NEON_2RM_VCVTAS:
|
||||
case NEON_2RM_VCVTNU:
|
||||
case NEON_2RM_VCVTNS:
|
||||
case NEON_2RM_VCVTPU:
|
||||
case NEON_2RM_VCVTPS:
|
||||
case NEON_2RM_VCVTMU:
|
||||
case NEON_2RM_VCVTMS:
|
||||
case NEON_2RM_VSWP:
|
||||
/* handled by decodetree */
|
||||
return 1;
|
||||
case NEON_2RM_VTRN:
|
||||
if (size == 2) {
|
||||
int n;
|
||||
for (n = 0; n < (q ? 4 : 2); n += 2) {
|
||||
tmp = neon_load_reg(rm, n);
|
||||
tmp2 = neon_load_reg(rd, n + 1);
|
||||
neon_store_reg(rm, n, tmp2);
|
||||
neon_store_reg(rd, n + 1, tmp);
|
||||
}
|
||||
} else {
|
||||
goto elementwise;
|
||||
}
|
||||
break;
|
||||
|
||||
default:
|
||||
elementwise:
|
||||
for (pass = 0; pass < (q ? 4 : 2); pass++) {
|
||||
tmp = neon_load_reg(rm, pass);
|
||||
switch (op) {
|
||||
case NEON_2RM_VTRN:
|
||||
tmp2 = neon_load_reg(rd, pass);
|
||||
switch (size) {
|
||||
case 0: gen_neon_trn_u8(tmp, tmp2); break;
|
||||
case 1: gen_neon_trn_u16(tmp, tmp2); break;
|
||||
default: abort();
|
||||
}
|
||||
neon_store_reg(rm, pass, tmp2);
|
||||
break;
|
||||
default:
|
||||
/* Reserved op values were caught by the
|
||||
* neon_2rm_sizes[] check earlier.
|
||||
*/
|
||||
abort();
|
||||
}
|
||||
neon_store_reg(rd, pass, tmp);
|
||||
}
|
||||
break;
|
||||
}
|
||||
} else {
|
||||
/* VTBL, VTBX, VDUP: handled by decodetree */
|
||||
return 1;
|
||||
}
|
||||
}
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int disas_coproc_insn(DisasContext *s, uint32_t insn)
|
||||
{
|
||||
int cpnum, is64, crn, crm, opc1, opc2, isread, rt, rt2;
|
||||
|
|
@ -8694,13 +8345,6 @@ static void disas_arm_insn(DisasContext *s, unsigned int insn)
|
|||
}
|
||||
/* fall back to legacy decoder */
|
||||
|
||||
if (((insn >> 25) & 7) == 1) {
|
||||
/* NEON Data processing. */
|
||||
if (disas_neon_data_insn(s, insn)) {
|
||||
goto illegal_op;
|
||||
}
|
||||
return;
|
||||
}
|
||||
if ((insn & 0x0e000f00) == 0x0c000100) {
|
||||
if (arm_dc_feature(s, ARM_FEATURE_IWMMXT)) {
|
||||
/* iWMMXt register transfer. */
|
||||
|
|
@ -8888,11 +8532,8 @@ static void disas_thumb2_insn(DisasContext *s, uint32_t insn)
|
|||
break;
|
||||
}
|
||||
if (((insn >> 24) & 3) == 3) {
|
||||
/* Translate into the equivalent ARM encoding. */
|
||||
insn = (insn & 0xe2ffffff) | ((insn & (1 << 28)) >> 4) | (1 << 28);
|
||||
if (disas_neon_data_insn(s, insn)) {
|
||||
goto illegal_op;
|
||||
}
|
||||
/* Neon DP, but failed disas_neon_dp() */
|
||||
goto illegal_op;
|
||||
} else if (((insn >> 8) & 0xe) == 10) {
|
||||
/* VFP, but failed disas_vfp. */
|
||||
goto illegal_op;
|
||||
|
|
|
|||
Loading…
Reference in New Issue