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target/arm: Convert TT

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Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20190904193059.26202-43-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Richard Henderson 2019-09-04 12:30:32 -07:00 committed by Peter Maydell
parent 35d240acf1
commit d449f174e8
2 changed files with 34 additions and 61 deletions
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5
target/arm/t32.decode
View File

@ -508,7 +508,10 @@ STRD_ri_t32 1110 1001 .110 .... .... .... ........ @ldstd_ri8 w=1 p=1
@ldrex_d .... .... .... rn:4 rt:4 rt2:4 .... .... \
&ldrex imm=0
STREX 1110 1000 0100 .... .... .... .... .... @strex_i
{
TT 1110 1000 0100 rn:4 1111 rd:4 A:1 T:1 000000
STREX 1110 1000 0100 .... .... .... .... .... @strex_i
}
STREXB 1110 1000 1100 .... .... 1111 0100 .... @strex_0
STREXH 1110 1000 1100 .... .... 1111 0101 .... @strex_0
STREXD_t32 1110 1000 1100 .... .... .... 0111 .... @strex_d

90
target/arm/translate.c
View File

@ -8495,6 +8495,33 @@ static bool trans_SG(DisasContext *s, arg_SG *a)
return true;
}
static bool trans_TT(DisasContext *s, arg_TT *a)
{
TCGv_i32 addr, tmp;
if (!arm_dc_feature(s, ARM_FEATURE_M) ||
!arm_dc_feature(s, ARM_FEATURE_V8)) {
return false;
}
if (a->rd == 13 || a->rd == 15 || a->rn == 15) {
/* We UNDEF for these UNPREDICTABLE cases */
unallocated_encoding(s);
return true;
}
if (a->A && !s->v8m_secure) {
/* This case is UNDEFINED. */
unallocated_encoding(s);
return true;
}
addr = load_reg(s, a->rn);
tmp = tcg_const_i32((a->A << 1) | a->T);
gen_helper_v7m_tt(tmp, cpu_env, addr, tmp);
tcg_temp_free_i32(addr);
store_reg(s, a->rd, tmp);
return true;
}
/*
* Load/store register index
*/
@ -10525,7 +10552,7 @@ static bool thumb_insn_is_16bit(DisasContext *s, uint32_t pc, uint32_t insn)
/* Translate a 32-bit thumb instruction. */
static void disas_thumb2_insn(DisasContext *s, uint32_t insn)
{
uint32_t rd, rn, rs;
uint32_t rn;
int op;
/*
@ -10569,70 +10596,13 @@ static void disas_thumb2_insn(DisasContext *s, uint32_t insn)
/* fall back to legacy decoder */
rn = (insn >> 16) & 0xf;
rs = (insn >> 12) & 0xf;
rd = (insn >> 8) & 0xf;
switch ((insn >> 25) & 0xf) {
case 0: case 1: case 2: case 3:
/* 16-bit instructions. Should never happen. */
abort();
case 4:
if (insn & (1 << 22)) {
/* 0b1110_100x_x1xx_xxxx_xxxx_xxxx_xxxx_xxxx
* - load/store doubleword, load/store exclusive, ldacq/strel,
* table branch, TT.
*/
if (insn & 0x01200000) {
/* load/store dual, in decodetree */
goto illegal_op;
} else if ((insn & (1 << 23)) == 0) {
/* 0b1110_1000_010x_xxxx_xxxx_xxxx_xxxx_xxxx
* - load/store exclusive word
* - TT (v8M only)
*/
if (rs == 15) {
if (!(insn & (1 << 20)) &&
arm_dc_feature(s, ARM_FEATURE_M) &&
arm_dc_feature(s, ARM_FEATURE_V8)) {
/* 0b1110_1000_0100_xxxx_1111_xxxx_xxxx_xxxx
* - TT (v8M only)
*/
bool alt = insn & (1 << 7);
TCGv_i32 addr, op, ttresp;
if ((insn & 0x3f) || rd == 13 || rd == 15 || rn == 15) {
/* we UNDEF for these UNPREDICTABLE cases */
goto illegal_op;
}
if (alt && !s->v8m_secure) {
goto illegal_op;
}
addr = load_reg(s, rn);
op = tcg_const_i32(extract32(insn, 6, 2));
ttresp = tcg_temp_new_i32();
gen_helper_v7m_tt(ttresp, cpu_env, addr, op);
tcg_temp_free_i32(addr);
tcg_temp_free_i32(op);
store_reg(s, rd, ttresp);
break;
}
goto illegal_op;
}
/* Load/store exclusive, in decodetree */
goto illegal_op;
} else if ((insn & (7 << 5)) == 0) {
/* Table Branch, in decodetree */
goto illegal_op;
} else {
/* Load/store exclusive, load-acq/store-rel, in decodetree */
goto illegal_op;
}
} else {
/* Load/store multiple, RFE, SRS, in decodetree */
goto illegal_op;
}
break;
/* All in decodetree */
goto illegal_op;
case 5:
/* All in decodetree */
goto illegal_op;