tcg: Split out tcg-target-reg-bits.h
Often, the only thing we need to know about the TCG host is the register size. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
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@ -32,6 +32,7 @@
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#include "qemu/plugin.h"
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#include "qemu/queue.h"
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#include "tcg/tcg-mo.h"
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#include "tcg-target-reg-bits.h"
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#include "tcg-target.h"
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#include "tcg/tcg-cond.h"
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#include "tcg/debug-assert.h"
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@ -44,17 +45,6 @@
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#define CPU_TEMP_BUF_NLONGS 128
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#define TCG_STATIC_FRAME_SIZE (CPU_TEMP_BUF_NLONGS * sizeof(long))
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/* Default target word size to pointer size. */
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#ifndef TCG_TARGET_REG_BITS
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# if UINTPTR_MAX == UINT32_MAX
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# define TCG_TARGET_REG_BITS 32
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# elif UINTPTR_MAX == UINT64_MAX
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# define TCG_TARGET_REG_BITS 64
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# else
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# error Unknown pointer size for tcg target
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# endif
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#endif
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#if TCG_TARGET_REG_BITS == 32
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typedef int32_t tcg_target_long;
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typedef uint32_t tcg_target_ulong;
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12
tcg/aarch64/tcg-target-reg-bits.h
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12
tcg/aarch64/tcg-target-reg-bits.h
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@ -0,0 +1,12 @@
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/* SPDX-License-Identifier: GPL-2.0-or-later */
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/*
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* Define target-specific register size
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* Copyright (c) 2023 Linaro
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*/
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#ifndef TCG_TARGET_REG_BITS_H
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#define TCG_TARGET_REG_BITS_H
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#define TCG_TARGET_REG_BITS 64
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#endif
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12
tcg/arm/tcg-target-reg-bits.h
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12
tcg/arm/tcg-target-reg-bits.h
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@ -0,0 +1,12 @@
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/* SPDX-License-Identifier: MIT */
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/*
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* Define target-specific register size
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* Copyright (c) 2023 Linaro
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*/
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#ifndef TCG_TARGET_REG_BITS_H
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#define TCG_TARGET_REG_BITS_H
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#define TCG_TARGET_REG_BITS 32
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#endif
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16
tcg/i386/tcg-target-reg-bits.h
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tcg/i386/tcg-target-reg-bits.h
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@ -0,0 +1,16 @@
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/* SPDX-License-Identifier: MIT */
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/*
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* Define target-specific register size
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* Copyright (c) 2008 Fabrice Bellard
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*/
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#ifndef TCG_TARGET_REG_BITS_H
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#define TCG_TARGET_REG_BITS_H
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#ifdef __x86_64__
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# define TCG_TARGET_REG_BITS 64
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#else
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# define TCG_TARGET_REG_BITS 32
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#endif
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#endif
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@ -30,11 +30,9 @@
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#define TCG_TARGET_INSN_UNIT_SIZE 1
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#ifdef __x86_64__
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# define TCG_TARGET_REG_BITS 64
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# define TCG_TARGET_NB_REGS 32
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# define MAX_CODE_GEN_BUFFER_SIZE (2 * GiB)
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#else
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# define TCG_TARGET_REG_BITS 32
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# define TCG_TARGET_NB_REGS 24
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# define MAX_CODE_GEN_BUFFER_SIZE UINT32_MAX
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#endif
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21
tcg/loongarch64/tcg-target-reg-bits.h
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tcg/loongarch64/tcg-target-reg-bits.h
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@ -0,0 +1,21 @@
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/* SPDX-License-Identifier: MIT */
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/*
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* Define target-specific register size
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* Copyright (c) 2021 WANG Xuerui <git@xen0n.name>
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*/
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#ifndef TCG_TARGET_REG_BITS_H
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#define TCG_TARGET_REG_BITS_H
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/*
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* Loongson removed the (incomplete) 32-bit support from kernel and toolchain
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* for the initial upstreaming of this architecture, so don't bother and just
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* support the LP64* ABI for now.
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*/
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#if defined(__loongarch64)
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# define TCG_TARGET_REG_BITS 64
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#else
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# error unsupported LoongArch register size
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#endif
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#endif
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@ -29,17 +29,6 @@
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#ifndef LOONGARCH_TCG_TARGET_H
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#define LOONGARCH_TCG_TARGET_H
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/*
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* Loongson removed the (incomplete) 32-bit support from kernel and toolchain
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* for the initial upstreaming of this architecture, so don't bother and just
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* support the LP64* ABI for now.
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*/
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#if defined(__loongarch64)
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# define TCG_TARGET_REG_BITS 64
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#else
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# error unsupported LoongArch register size
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#endif
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#define TCG_TARGET_INSN_UNIT_SIZE 4
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#define TCG_TARGET_NB_REGS 32
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tcg/mips/tcg-target-reg-bits.h
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tcg/mips/tcg-target-reg-bits.h
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@ -0,0 +1,18 @@
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/* SPDX-License-Identifier: MIT */
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/*
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* Define target-specific register size
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* Copyright (c) 2008-2009 Arnaud Patard <arnaud.patard@rtp-net.org>
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*/
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#ifndef TCG_TARGET_REG_BITS_H
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#define TCG_TARGET_REG_BITS_H
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#if _MIPS_SIM == _ABIO32
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# define TCG_TARGET_REG_BITS 32
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#elif _MIPS_SIM == _ABIN32 || _MIPS_SIM == _ABI64
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# define TCG_TARGET_REG_BITS 64
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#else
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# error "Unknown ABI"
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#endif
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#endif
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@ -27,14 +27,6 @@
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#ifndef MIPS_TCG_TARGET_H
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#define MIPS_TCG_TARGET_H
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#if _MIPS_SIM == _ABIO32
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# define TCG_TARGET_REG_BITS 32
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#elif _MIPS_SIM == _ABIN32 || _MIPS_SIM == _ABI64
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# define TCG_TARGET_REG_BITS 64
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#else
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# error "Unknown ABI"
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#endif
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#define TCG_TARGET_INSN_UNIT_SIZE 4
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#define TCG_TARGET_NB_REGS 32
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16
tcg/ppc/tcg-target-reg-bits.h
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tcg/ppc/tcg-target-reg-bits.h
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@ -0,0 +1,16 @@
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/* SPDX-License-Identifier: MIT */
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/*
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* Define target-specific register size
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* Copyright (c) 2008 Fabrice Bellard
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*/
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#ifndef TCG_TARGET_REG_BITS_H
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#define TCG_TARGET_REG_BITS_H
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#ifdef _ARCH_PPC64
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# define TCG_TARGET_REG_BITS 64
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#else
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# define TCG_TARGET_REG_BITS 32
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#endif
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#endif
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@ -25,11 +25,6 @@
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#ifndef PPC_TCG_TARGET_H
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#define PPC_TCG_TARGET_H
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#ifdef _ARCH_PPC64
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# define TCG_TARGET_REG_BITS 64
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#else
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# define TCG_TARGET_REG_BITS 32
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#endif
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#define MAX_CODE_GEN_BUFFER_SIZE ((size_t)-1)
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#define TCG_TARGET_NB_REGS 64
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tcg/riscv/tcg-target-reg-bits.h
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tcg/riscv/tcg-target-reg-bits.h
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/* SPDX-License-Identifier: MIT */
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/*
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* Define target-specific register size
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* Copyright (c) 2018 SiFive, Inc
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*/
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#ifndef TCG_TARGET_REG_BITS_H
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#define TCG_TARGET_REG_BITS_H
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/*
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* We don't support oversize guests.
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* Since we will only build tcg once, this in turn requires a 64-bit host.
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*/
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#if __riscv_xlen != 64
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#error "unsupported code generation mode"
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#endif
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#define TCG_TARGET_REG_BITS 64
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#endif
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@ -25,15 +25,6 @@
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#ifndef RISCV_TCG_TARGET_H
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#define RISCV_TCG_TARGET_H
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/*
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* We don't support oversize guests.
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* Since we will only build tcg once, this in turn requires a 64-bit host.
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*/
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#if __riscv_xlen != 64
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#error "unsupported code generation mode"
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#endif
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#define TCG_TARGET_REG_BITS 64
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#define TCG_TARGET_INSN_UNIT_SIZE 4
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#define TCG_TARGET_NB_REGS 32
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#define MAX_CODE_GEN_BUFFER_SIZE ((size_t)-1)
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tcg/s390x/tcg-target-reg-bits.h
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tcg/s390x/tcg-target-reg-bits.h
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@ -0,0 +1,17 @@
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/* SPDX-License-Identifier: MIT */
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/*
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* Define target-specific register size
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* Copyright (c) 2009 Ulrich Hecht <uli@suse.de>
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*/
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#ifndef TCG_TARGET_REG_BITS_H
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#define TCG_TARGET_REG_BITS_H
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/* We only support generating code for 64-bit mode. */
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#if UINTPTR_MAX == UINT64_MAX
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# define TCG_TARGET_REG_BITS 64
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#else
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# error "unsupported code generation mode"
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#endif
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#endif
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@ -24,11 +24,6 @@
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* THE SOFTWARE.
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*/
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/* We only support generating code for 64-bit mode. */
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#if TCG_TARGET_REG_BITS != 64
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#error "unsupported code generation mode"
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#endif
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#include "../tcg-ldst.c.inc"
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#include "../tcg-pool.c.inc"
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#include "elf.h"
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tcg/sparc64/tcg-target-reg-bits.h
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12
tcg/sparc64/tcg-target-reg-bits.h
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/* SPDX-License-Identifier: MIT */
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/*
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* Define target-specific register size
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* Copyright (c) 2023 Linaro
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*/
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#ifndef TCG_TARGET_REG_BITS_H
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#define TCG_TARGET_REG_BITS_H
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#define TCG_TARGET_REG_BITS 64
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#endif
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tcg/tci/tcg-target-reg-bits.h
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tcg/tci/tcg-target-reg-bits.h
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/* SPDX-License-Identifier: MIT */
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/*
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* Define target-specific register size
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* Copyright (c) 2009, 2011 Stefan Weil
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*/
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#ifndef TCG_TARGET_REG_BITS_H
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#define TCG_TARGET_REG_BITS_H
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#if UINTPTR_MAX == UINT32_MAX
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# define TCG_TARGET_REG_BITS 32
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#elif UINTPTR_MAX == UINT64_MAX
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# define TCG_TARGET_REG_BITS 64
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#else
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# error Unknown pointer size for tci target
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#endif
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#endif
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#define TCG_TARGET_INSN_UNIT_SIZE 4
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#define MAX_CODE_GEN_BUFFER_SIZE ((size_t)-1)
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#if UINTPTR_MAX == UINT32_MAX
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# define TCG_TARGET_REG_BITS 32
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#elif UINTPTR_MAX == UINT64_MAX
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# define TCG_TARGET_REG_BITS 64
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#else
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# error Unknown pointer size for tci target
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#endif
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/* Optional instructions. */
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#define TCG_TARGET_HAS_bswap16_i32 1
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