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target/arm: Implement SVE2 integer pairwise add and accumulate long 

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210525010358.152808-4-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Richard Henderson 2021-05-24 18:02:29 -07:00 committed by Peter Maydell
parent 5dad1ba52f
commit d4b1e59d98
4 changed files with 102 additions and 0 deletions
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14
target/arm/helper-sve.h
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@ -158,6 +158,20 @@ DEF_HELPER_FLAGS_5(sve_umulh_zpzz_s, TCG_CALL_NO_RWG,
DEF_HELPER_FLAGS_5(sve_umulh_zpzz_d, TCG_CALL_NO_RWG,
void, ptr, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_5(sve2_sadalp_zpzz_h, TCG_CALL_NO_RWG,
void, ptr, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_5(sve2_sadalp_zpzz_s, TCG_CALL_NO_RWG,
void, ptr, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_5(sve2_sadalp_zpzz_d, TCG_CALL_NO_RWG,
void, ptr, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_5(sve2_uadalp_zpzz_h, TCG_CALL_NO_RWG,
void, ptr, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_5(sve2_uadalp_zpzz_s, TCG_CALL_NO_RWG,
void, ptr, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_5(sve2_uadalp_zpzz_d, TCG_CALL_NO_RWG,
void, ptr, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_5(sve_sdiv_zpzz_s, TCG_CALL_NO_RWG,
void, ptr, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_5(sve_sdiv_zpzz_d, TCG_CALL_NO_RWG,

5
target/arm/sve.decode
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@ -1100,3 +1100,8 @@ MUL_zzz 00000100 .. 1 ..... 0110 00 ..... ..... @rd_rn_rm
SMULH_zzz 00000100 .. 1 ..... 0110 10 ..... ..... @rd_rn_rm
UMULH_zzz 00000100 .. 1 ..... 0110 11 ..... ..... @rd_rn_rm
PMUL_zzz 00000100 00 1 ..... 0110 01 ..... ..... @rd_rn_rm_e0
### SVE2 Integer - Predicated
SADALP_zpzz 01000100 .. 000 100 101 ... ..... ..... @rdm_pg_rn
UADALP_zpzz 01000100 .. 000 101 101 ... ..... ..... @rdm_pg_rn

44
target/arm/sve_helper.c
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@ -517,6 +517,50 @@ DO_ZPZZ_D(sve_asr_zpzz_d, int64_t, DO_ASR)
DO_ZPZZ_D(sve_lsr_zpzz_d, uint64_t, DO_LSR)
DO_ZPZZ_D(sve_lsl_zpzz_d, uint64_t, DO_LSL)
static inline uint16_t do_sadalp_h(int16_t n, int16_t m)
{
int8_t n1 = n, n2 = n >> 8;
return m + n1 + n2;
}
static inline uint32_t do_sadalp_s(int32_t n, int32_t m)
{
int16_t n1 = n, n2 = n >> 16;
return m + n1 + n2;
}
static inline uint64_t do_sadalp_d(int64_t n, int64_t m)
{
int32_t n1 = n, n2 = n >> 32;
return m + n1 + n2;
}
DO_ZPZZ(sve2_sadalp_zpzz_h, int16_t, H1_2, do_sadalp_h)
DO_ZPZZ(sve2_sadalp_zpzz_s, int32_t, H1_4, do_sadalp_s)
DO_ZPZZ_D(sve2_sadalp_zpzz_d, int64_t, do_sadalp_d)
static inline uint16_t do_uadalp_h(uint16_t n, uint16_t m)
{
uint8_t n1 = n, n2 = n >> 8;
return m + n1 + n2;
}
static inline uint32_t do_uadalp_s(uint32_t n, uint32_t m)
{
uint16_t n1 = n, n2 = n >> 16;
return m + n1 + n2;
}
static inline uint64_t do_uadalp_d(uint64_t n, uint64_t m)
{
uint32_t n1 = n, n2 = n >> 32;
return m + n1 + n2;
}
DO_ZPZZ(sve2_uadalp_zpzz_h, uint16_t, H1_2, do_uadalp_h)
DO_ZPZZ(sve2_uadalp_zpzz_s, uint32_t, H1_4, do_uadalp_s)
DO_ZPZZ_D(sve2_uadalp_zpzz_d, uint64_t, do_uadalp_d)
#undef DO_ZPZZ
#undef DO_ZPZZ_D

39
target/arm/translate-sve.c
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@ -5845,3 +5845,42 @@ static bool trans_PMUL_zzz(DisasContext *s, arg_rrr_esz *a)
{
return do_sve2_zzz_ool(s, a, gen_helper_gvec_pmul_b);
}
/*
* SVE2 Integer - Predicated
*/
static bool do_sve2_zpzz_ool(DisasContext *s, arg_rprr_esz *a,
gen_helper_gvec_4 *fn)
{
if (!dc_isar_feature(aa64_sve2, s)) {
return false;
}
return do_zpzz_ool(s, a, fn);
}
static bool trans_SADALP_zpzz(DisasContext *s, arg_rprr_esz *a)
{
static gen_helper_gvec_4 * const fns[3] = {
gen_helper_sve2_sadalp_zpzz_h,
gen_helper_sve2_sadalp_zpzz_s,
gen_helper_sve2_sadalp_zpzz_d,
};
if (a->esz == 0) {
return false;
}
return do_sve2_zpzz_ool(s, a, fns[a->esz - 1]);
}
static bool trans_UADALP_zpzz(DisasContext *s, arg_rprr_esz *a)
{
static gen_helper_gvec_4 * const fns[3] = {
gen_helper_sve2_uadalp_zpzz_h,
gen_helper_sve2_uadalp_zpzz_s,
gen_helper_sve2_uadalp_zpzz_d,
};
if (a->esz == 0) {
return false;
}
return do_sve2_zpzz_ool(s, a, fns[a->esz - 1]);
}