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xilinx_axienet: Implement R_IS behaviour

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The interrupt status register R_IS is the standard clear-on-write behaviour.
This was unimplemented and defaulting to updating the register to the written
value. Implemented clear-on-write.

Reported-by: Jason Wu <huanyu@xilinx.com>
Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@gmail.com>
This commit is contained in:
Peter Crosthwaite 2012-12-05 16:53:42 +10:00 committed by Edgar E. Iglesias
parent 16c6c80ac3
commit d4d230da08
1 changed files with 4 additions and 0 deletions
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4
hw/xilinx_axienet.c
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@ -591,6 +591,10 @@ static void enet_write(void *opaque, hwaddr addr,
s->maddr[s->fmi & 3][addr & 1] = value; s->maddr[s->fmi & 3][addr & 1] = value;
break; break;
case R_IS:
s->regs[addr] &= ~value;
break;
case 0x8000 ... 0x83ff: case 0x8000 ... 0x83ff:
s->ext_mtable[addr - 0x8000] = value; s->ext_mtable[addr - 0x8000] = value;
break; break;