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target-m68k: avoid using cpu_single_env 

Pass around CPUState instead of using global cpu_single_env.

Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
This commit is contained in:
Blue Swirl 2012-09-08 10:48:20 +00:00
parent 3187114152
commit d4d79bb144
1 changed files with 140 additions and 130 deletions
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270
target-m68k/translate.c
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@ -150,18 +150,24 @@ static void *gen_throws_exception;
#define OS_SINGLE 4
#define OS_DOUBLE 5
typedef void (*disas_proc)(DisasContext *, uint16_t);
typedef void (*disas_proc)(CPUM68KState *env, DisasContext *s, uint16_t insn);
#ifdef DEBUG_DISPATCH
#define DISAS_INSN(name) \
static void real_disas_##name (DisasContext *s, uint16_t insn); \
static void disas_##name (DisasContext *s, uint16_t insn) { \
qemu_log("Dispatch " #name "\n"); \
real_disas_##name(s, insn); } \
static void real_disas_##name (DisasContext *s, uint16_t insn)
#define DISAS_INSN(name) \
static void real_disas_##name(CPUM68KState *env, DisasContext *s, \
uint16_t insn); \
static void disas_##name(CPUM68KState *env, DisasContext *s, \
uint16_t insn) \
{ \
qemu_log("Dispatch " #name "\n"); \
real_disas_##name(s, env, insn); \
} \
static void real_disas_##name(CPUM68KState *env, DisasContext *s, \
uint16_t insn)
#else
#define DISAS_INSN(name) \
static void disas_##name (DisasContext *s, uint16_t insn)
#define DISAS_INSN(name) \
static void disas_##name(CPUM68KState *env, DisasContext *s, \
uint16_t insn)
#endif
/* Generate a load from the specified address. Narrow values are
@ -257,12 +263,12 @@ static TCGv gen_ldst(DisasContext *s, int opsize, TCGv addr, TCGv val,
}
/* Read a 32-bit immediate constant. */
static inline uint32_t read_im32(DisasContext *s)
static inline uint32_t read_im32(CPUM68KState *env, DisasContext *s)
{
uint32_t im;
im = ((uint32_t)cpu_lduw_code(cpu_single_env, s->pc)) << 16;
im = ((uint32_t)cpu_lduw_code(env, s->pc)) << 16;
s->pc += 2;
im |= cpu_lduw_code(cpu_single_env, s->pc);
im |= cpu_lduw_code(env, s->pc);
s->pc += 2;
return im;
}
@ -288,7 +294,8 @@ static TCGv gen_addr_index(uint16_t ext, TCGv tmp)
/* Handle a base + index + displacement effective addresss.
A NULL_QREG base means pc-relative. */
static TCGv gen_lea_indexed(DisasContext *s, int opsize, TCGv base)
static TCGv gen_lea_indexed(CPUM68KState *env, DisasContext *s, int opsize,
TCGv base)
{
uint32_t offset;
uint16_t ext;
@ -297,7 +304,7 @@ static TCGv gen_lea_indexed(DisasContext *s, int opsize, TCGv base)
uint32_t bd, od;
offset = s->pc;
ext = cpu_lduw_code(cpu_single_env, s->pc);
ext = cpu_lduw_code(env, s->pc);
s->pc += 2;
if ((ext & 0x800) == 0 && !m68k_feature(s->env, M68K_FEATURE_WORD_INDEX))
@ -311,10 +318,10 @@ static TCGv gen_lea_indexed(DisasContext *s, int opsize, TCGv base)
if ((ext & 0x30) > 0x10) {
/* base displacement */
if ((ext & 0x30) == 0x20) {
bd = (int16_t)cpu_lduw_code(cpu_single_env, s->pc);
bd = (int16_t)cpu_lduw_code(env, s->pc);
s->pc += 2;
} else {
bd = read_im32(s);
bd = read_im32(env, s);
}
} else {
bd = 0;
@ -360,10 +367,10 @@ static TCGv gen_lea_indexed(DisasContext *s, int opsize, TCGv base)
if ((ext & 3) > 1) {
/* outer displacement */
if ((ext & 3) == 2) {
od = (int16_t)cpu_lduw_code(cpu_single_env, s->pc);
od = (int16_t)cpu_lduw_code(env, s->pc);
s->pc += 2;
} else {
od = read_im32(s);
od = read_im32(env, s);
}
} else {
od = 0;
@ -492,7 +499,8 @@ static inline TCGv gen_extend(TCGv val, int opsize, int sign)
/* Generate code for an "effective address". Does not adjust the base
register for autoincrement addressing modes. */
static TCGv gen_lea(DisasContext *s, uint16_t insn, int opsize)
static TCGv gen_lea(CPUM68KState *env, DisasContext *s, uint16_t insn,
int opsize)
{
TCGv reg;
TCGv tmp;
@ -514,29 +522,29 @@ static TCGv gen_lea(DisasContext *s, uint16_t insn, int opsize)
case 5: /* Indirect displacement. */
reg = AREG(insn, 0);
tmp = tcg_temp_new();
ext = cpu_lduw_code(cpu_single_env, s->pc);
ext = cpu_lduw_code(env, s->pc);
s->pc += 2;
tcg_gen_addi_i32(tmp, reg, (int16_t)ext);
return tmp;
case 6: /* Indirect index + displacement. */
reg = AREG(insn, 0);
return gen_lea_indexed(s, opsize, reg);
return gen_lea_indexed(env, s, opsize, reg);
case 7: /* Other */
switch (insn & 7) {
case 0: /* Absolute short. */
offset = cpu_ldsw_code(cpu_single_env, s->pc);
offset = cpu_ldsw_code(env, s->pc);
s->pc += 2;
return tcg_const_i32(offset);
case 1: /* Absolute long. */
offset = read_im32(s);
offset = read_im32(env, s);
return tcg_const_i32(offset);
case 2: /* pc displacement */
offset = s->pc;
offset += cpu_ldsw_code(cpu_single_env, s->pc);
offset += cpu_ldsw_code(env, s->pc);
s->pc += 2;
return tcg_const_i32(offset);
case 3: /* pc index+displacement. */
return gen_lea_indexed(s, opsize, NULL_QREG);
return gen_lea_indexed(env, s, opsize, NULL_QREG);
case 4: /* Immediate. */
default:
return NULL_QREG;
@ -548,15 +556,16 @@ static TCGv gen_lea(DisasContext *s, uint16_t insn, int opsize)
/* Helper function for gen_ea. Reuse the computed address between the
for read/write operands. */
static inline TCGv gen_ea_once(DisasContext *s, uint16_t insn, int opsize,
TCGv val, TCGv *addrp, ea_what what)
static inline TCGv gen_ea_once(CPUM68KState *env, DisasContext *s,
uint16_t insn, int opsize, TCGv val,
TCGv *addrp, ea_what what)
{
TCGv tmp;
if (addrp && what == EA_STORE) {
tmp = *addrp;
} else {
tmp = gen_lea(s, insn, opsize);
tmp = gen_lea(env, s, insn, opsize);
if (IS_NULL_QREG(tmp))
return tmp;
if (addrp)
@ -568,8 +577,8 @@ static inline TCGv gen_ea_once(DisasContext *s, uint16_t insn, int opsize,
/* Generate code to load/store a value ito/from an EA. If VAL > 0 this is
a write otherwise it is a read (0 == sign extend, -1 == zero extend).
ADDRP is non-null for readwrite operands. */
static TCGv gen_ea(DisasContext *s, uint16_t insn, int opsize, TCGv val,
TCGv *addrp, ea_what what)
static TCGv gen_ea(CPUM68KState *env, DisasContext *s, uint16_t insn,
int opsize, TCGv val, TCGv *addrp, ea_what what)
{
TCGv reg;
TCGv result;
@ -609,7 +618,7 @@ static TCGv gen_ea(DisasContext *s, uint16_t insn, int opsize, TCGv val,
if (addrp && what == EA_STORE) {
tmp = *addrp;
} else {
tmp = gen_lea(s, insn, opsize);
tmp = gen_lea(env, s, insn, opsize);
if (IS_NULL_QREG(tmp))
return tmp;
if (addrp)
@ -626,35 +635,35 @@ static TCGv gen_ea(DisasContext *s, uint16_t insn, int opsize, TCGv val,
return result;
case 5: /* Indirect displacement. */
case 6: /* Indirect index + displacement. */
return gen_ea_once(s, insn, opsize, val, addrp, what);
return gen_ea_once(env, s, insn, opsize, val, addrp, what);
case 7: /* Other */
switch (insn & 7) {
case 0: /* Absolute short. */
case 1: /* Absolute long. */
case 2: /* pc displacement */
case 3: /* pc index+displacement. */
return gen_ea_once(s, insn, opsize, val, addrp, what);
return gen_ea_once(env, s, insn, opsize, val, addrp, what);
case 4: /* Immediate. */
/* Sign extend values for consistency. */
switch (opsize) {
case OS_BYTE:
if (what == EA_LOADS) {
offset = cpu_ldsb_code(cpu_single_env, s->pc + 1);
offset = cpu_ldsb_code(env, s->pc + 1);
} else {
offset = cpu_ldub_code(cpu_single_env, s->pc + 1);
offset = cpu_ldub_code(env, s->pc + 1);
}
s->pc += 2;
break;
case OS_WORD:
if (what == EA_LOADS) {
offset = cpu_ldsw_code(cpu_single_env, s->pc);
offset = cpu_ldsw_code(env, s->pc);
} else {
offset = cpu_lduw_code(cpu_single_env, s->pc);
offset = cpu_lduw_code(env, s->pc);
}
s->pc += 2;
break;
case OS_LONG:
offset = read_im32(s);
offset = read_im32(env, s);
break;
default:
qemu_assert(0, "Bad immediate operand");
@ -825,20 +834,21 @@ static inline void gen_addr_fault(DisasContext *s)
gen_exception(s, s->insn_pc, EXCP_ADDRESS);
}
#define SRC_EA(result, opsize, op_sign, addrp) do { \
result = gen_ea(s, insn, opsize, NULL_QREG, addrp, op_sign ? EA_LOADS : EA_LOADU); \
if (IS_NULL_QREG(result)) { \
gen_addr_fault(s); \
return; \
} \
#define SRC_EA(env, result, opsize, op_sign, addrp) do { \
result = gen_ea(env, s, insn, opsize, NULL_QREG, addrp, \
op_sign ? EA_LOADS : EA_LOADU); \
if (IS_NULL_QREG(result)) { \
gen_addr_fault(s); \
return; \
} \
} while (0)
#define DEST_EA(insn, opsize, val, addrp) do { \
TCGv ea_result = gen_ea(s, insn, opsize, val, addrp, EA_STORE); \
if (IS_NULL_QREG(ea_result)) { \
gen_addr_fault(s); \
return; \
} \
#define DEST_EA(env, insn, opsize, val, addrp) do { \
TCGv ea_result = gen_ea(env, s, insn, opsize, val, addrp, EA_STORE); \
if (IS_NULL_QREG(ea_result)) { \
gen_addr_fault(s); \
return; \
} \
} while (0)
/* Generate a jump to an immediate address. */
@ -874,8 +884,7 @@ DISAS_INSN(undef_fpu)
DISAS_INSN(undef)
{
gen_exception(s, s->pc - 2, EXCP_UNSUPPORTED);
cpu_abort(cpu_single_env, "Illegal instruction: %04x @ %08x",
insn, s->pc - 2);
cpu_abort(env, "Illegal instruction: %04x @ %08x", insn, s->pc - 2);
}
DISAS_INSN(mulw)
@ -892,7 +901,7 @@ DISAS_INSN(mulw)
tcg_gen_ext16s_i32(tmp, reg);
else
tcg_gen_ext16u_i32(tmp, reg);
SRC_EA(src, OS_WORD, sign, NULL);
SRC_EA(env, src, OS_WORD, sign, NULL);
tcg_gen_mul_i32(tmp, tmp, src);
tcg_gen_mov_i32(reg, tmp);
/* Unlike m68k, coldfire always clears the overflow bit. */
@ -913,7 +922,7 @@ DISAS_INSN(divw)
} else {
tcg_gen_ext16u_i32(QREG_DIV1, reg);
}
SRC_EA(src, OS_WORD, sign, NULL);
SRC_EA(env, src, OS_WORD, sign, NULL);
tcg_gen_mov_i32(QREG_DIV2, src);
if (sign) {
gen_helper_divs(cpu_env, tcg_const_i32(1));
@ -936,7 +945,7 @@ DISAS_INSN(divl)
TCGv reg;
uint16_t ext;
ext = cpu_lduw_code(cpu_single_env, s->pc);
ext = cpu_lduw_code(env, s->pc);
s->pc += 2;
if (ext & 0x87f8) {
gen_exception(s, s->pc - 4, EXCP_UNSUPPORTED);
@ -945,7 +954,7 @@ DISAS_INSN(divl)
num = DREG(ext, 12);
reg = DREG(ext, 0);
tcg_gen_mov_i32(QREG_DIV1, num);
SRC_EA(den, OS_LONG, 0, NULL);
SRC_EA(env, den, OS_LONG, 0, NULL);
tcg_gen_mov_i32(QREG_DIV2, den);
if (ext & 0x0800) {
gen_helper_divs(cpu_env, tcg_const_i32(0));
@ -975,11 +984,11 @@ DISAS_INSN(addsub)
reg = DREG(insn, 9);
dest = tcg_temp_new();
if (insn & 0x100) {
SRC_EA(tmp, OS_LONG, 0, &addr);
SRC_EA(env, tmp, OS_LONG, 0, &addr);
src = reg;
} else {
tmp = reg;
SRC_EA(src, OS_LONG, 0, NULL);
SRC_EA(env, src, OS_LONG, 0, NULL);
}
if (add) {
tcg_gen_add_i32(dest, tmp, src);
@ -992,7 +1001,7 @@ DISAS_INSN(addsub)
}
gen_update_cc_add(dest, src);
if (insn & 0x100) {
DEST_EA(insn, OS_LONG, dest, &addr);
DEST_EA(env, insn, OS_LONG, dest, &addr);
} else {
tcg_gen_mov_i32(reg, dest);
}
@ -1022,7 +1031,7 @@ DISAS_INSN(bitop_reg)
else
opsize = OS_LONG;
op = (insn >> 6) & 3;
SRC_EA(src1, opsize, 0, op ? &addr: NULL);
SRC_EA(env, src1, opsize, 0, op ? &addr: NULL);
src2 = DREG(insn, 9);
dest = tcg_temp_new();
@ -1057,7 +1066,7 @@ DISAS_INSN(bitop_reg)
break;
}
if (op)
DEST_EA(insn, opsize, dest, &addr);
DEST_EA(env, insn, opsize, dest, &addr);
}
DISAS_INSN(sats)
@ -1088,9 +1097,9 @@ DISAS_INSN(movem)
TCGv tmp;
int is_load;
mask = cpu_lduw_code(cpu_single_env, s->pc);
mask = cpu_lduw_code(env, s->pc);
s->pc += 2;
tmp = gen_lea(s, insn, OS_LONG);
tmp = gen_lea(env, s, insn, OS_LONG);
if (IS_NULL_QREG(tmp)) {
gen_addr_fault(s);
return;
@ -1132,14 +1141,14 @@ DISAS_INSN(bitop_im)
opsize = OS_LONG;
op = (insn >> 6) & 3;
bitnum = cpu_lduw_code(cpu_single_env, s->pc);
bitnum = cpu_lduw_code(env, s->pc);
s->pc += 2;
if (bitnum & 0xff00) {
disas_undef(s, insn);
disas_undef(env, s, insn);
return;
}
SRC_EA(src1, opsize, 0, op ? &addr: NULL);
SRC_EA(env, src1, opsize, 0, op ? &addr: NULL);
gen_flush_flags(s);
if (opsize == OS_BYTE)
@ -1174,7 +1183,7 @@ DISAS_INSN(bitop_im)
default: /* btst */
break;
}
DEST_EA(insn, opsize, tmp, &addr);
DEST_EA(env, insn, opsize, tmp, &addr);
}
}
@ -1187,8 +1196,8 @@ DISAS_INSN(arith_im)
TCGv addr;
op = (insn >> 9) & 7;
SRC_EA(src1, OS_LONG, 0, (op == 6) ? NULL : &addr);
im = read_im32(s);
SRC_EA(env, src1, OS_LONG, 0, (op == 6) ? NULL : &addr);
im = read_im32(env, s);
dest = tcg_temp_new();
switch (op) {
case 0: /* ori */
@ -1227,7 +1236,7 @@ DISAS_INSN(arith_im)
abort();
}
if (op != 6) {
DEST_EA(insn, OS_LONG, dest, &addr);
DEST_EA(env, insn, OS_LONG, dest, &addr);
}
}
@ -1259,7 +1268,7 @@ DISAS_INSN(move)
default:
abort();
}
SRC_EA(src, opsize, 1, NULL);
SRC_EA(env, src, opsize, 1, NULL);
op = (insn >> 6) & 7;
if (op == 1) {
/* movea */
@ -1270,7 +1279,7 @@ DISAS_INSN(move)
/* normal move */
uint16_t dest_ea;
dest_ea = ((insn >> 9) & 7) | (op << 3);
DEST_EA(dest_ea, opsize, src, NULL);
DEST_EA(env, dest_ea, opsize, src, NULL);
/* This will be correct because loads sign extend. */
gen_logic_cc(s, src);
}
@ -1291,7 +1300,7 @@ DISAS_INSN(lea)
TCGv tmp;
reg = AREG(insn, 9);
tmp = gen_lea(s, insn, OS_LONG);
tmp = gen_lea(env, s, insn, OS_LONG);
if (IS_NULL_QREG(tmp)) {
gen_addr_fault(s);
return;
@ -1316,7 +1325,7 @@ DISAS_INSN(clr)
default:
abort();
}
DEST_EA(insn, opsize, tcg_const_i32(0), NULL);
DEST_EA(env, insn, opsize, tcg_const_i32(0), NULL);
gen_logic_cc(s, tcg_const_i32(0));
}
@ -1365,7 +1374,8 @@ static void gen_set_sr_im(DisasContext *s, uint16_t val, int ccr_only)
}
}
static void gen_set_sr(DisasContext *s, uint16_t insn, int ccr_only)
static void gen_set_sr(CPUM68KState *env, DisasContext *s, uint16_t insn,
int ccr_only)
{
TCGv tmp;
TCGv reg;
@ -1385,17 +1395,17 @@ static void gen_set_sr(DisasContext *s, uint16_t insn, int ccr_only)
else if ((insn & 0x3f) == 0x3c)
{
uint16_t val;
val = cpu_lduw_code(cpu_single_env, s->pc);
val = cpu_lduw_code(env, s->pc);
s->pc += 2;
gen_set_sr_im(s, val, ccr_only);
}
else
disas_undef(s, insn);
disas_undef(env, s, insn);
}
DISAS_INSN(move_to_ccr)
{
gen_set_sr(s, insn, 1);
gen_set_sr(env, s, insn, 1);
}
DISAS_INSN(not)
@ -1426,7 +1436,7 @@ DISAS_INSN(pea)
{
TCGv tmp;
tmp = gen_lea(s, insn, OS_LONG);
tmp = gen_lea(env, s, insn, OS_LONG);
if (IS_NULL_QREG(tmp)) {
gen_addr_fault(s);
return;
@ -1472,7 +1482,7 @@ DISAS_INSN(tst)
default:
abort();
}
SRC_EA(tmp, opsize, 1, NULL);
SRC_EA(env, tmp, opsize, 1, NULL);
gen_logic_cc(s, tmp);
}
@ -1494,10 +1504,10 @@ DISAS_INSN(tas)
TCGv addr;
dest = tcg_temp_new();
SRC_EA(src1, OS_BYTE, 1, &addr);
SRC_EA(env, src1, OS_BYTE, 1, &addr);
gen_logic_cc(s, src1);
tcg_gen_ori_i32(dest, src1, 0x80);
DEST_EA(insn, OS_BYTE, dest, &addr);
DEST_EA(env, insn, OS_BYTE, dest, &addr);
}
DISAS_INSN(mull)
@ -1509,14 +1519,14 @@ DISAS_INSN(mull)
/* The upper 32 bits of the product are discarded, so
muls.l and mulu.l are functionally equivalent. */
ext = cpu_lduw_code(cpu_single_env, s->pc);
ext = cpu_lduw_code(env, s->pc);
s->pc += 2;
if (ext & 0x87ff) {
gen_exception(s, s->pc - 4, EXCP_UNSUPPORTED);
return;
}
reg = DREG(ext, 12);
SRC_EA(src1, OS_LONG, 0, NULL);
SRC_EA(env, src1, OS_LONG, 0, NULL);
dest = tcg_temp_new();
tcg_gen_mul_i32(dest, src1, reg);
tcg_gen_mov_i32(reg, dest);
@ -1530,7 +1540,7 @@ DISAS_INSN(link)
TCGv reg;
TCGv tmp;
offset = cpu_ldsw_code(cpu_single_env, s->pc);
offset = cpu_ldsw_code(env, s->pc);
s->pc += 2;
reg = AREG(insn, 0);
tmp = tcg_temp_new();
@ -1574,7 +1584,7 @@ DISAS_INSN(jump)
/* Load the target address first to ensure correct exception
behavior. */
tmp = gen_lea(s, insn, OS_LONG);
tmp = gen_lea(env, s, insn, OS_LONG);
if (IS_NULL_QREG(tmp)) {
gen_addr_fault(s);
return;
@ -1594,7 +1604,7 @@ DISAS_INSN(addsubq)
int val;
TCGv addr;
SRC_EA(src1, OS_LONG, 0, &addr);
SRC_EA(env, src1, OS_LONG, 0, &addr);
val = (insn >> 9) & 7;
if (val == 0)
val = 8;
@ -1621,7 +1631,7 @@ DISAS_INSN(addsubq)
}
gen_update_cc_add(dest, src2);
}
DEST_EA(insn, OS_LONG, dest, &addr);
DEST_EA(env, insn, OS_LONG, dest, &addr);
}
DISAS_INSN(tpf)
@ -1636,7 +1646,7 @@ DISAS_INSN(tpf)
case 4: /* No extension words. */
break;
default:
disas_undef(s, insn);
disas_undef(env, s, insn);
}
}
@ -1651,10 +1661,10 @@ DISAS_INSN(branch)
op = (insn >> 8) & 0xf;
offset = (int8_t)insn;
if (offset == 0) {
offset = cpu_ldsw_code(cpu_single_env, s->pc);
offset = cpu_ldsw_code(env, s->pc);
s->pc += 2;
} else if (offset == -1) {
offset = read_im32(s);
offset = read_im32(env, s);
}
if (op == 1) {
/* bsr */
@ -1693,7 +1703,7 @@ DISAS_INSN(mvzs)
opsize = OS_WORD;
else
opsize = OS_BYTE;
SRC_EA(src, opsize, (insn & 0x80) == 0, NULL);
SRC_EA(env, src, opsize, (insn & 0x80) == 0, NULL);
reg = DREG(insn, 9);
tcg_gen_mov_i32(reg, src);
gen_logic_cc(s, src);
@ -1709,11 +1719,11 @@ DISAS_INSN(or)
reg = DREG(insn, 9);
dest = tcg_temp_new();
if (insn & 0x100) {
SRC_EA(src, OS_LONG, 0, &addr);
SRC_EA(env, src, OS_LONG, 0, &addr);
tcg_gen_or_i32(dest, src, reg);
DEST_EA(insn, OS_LONG, dest, &addr);
DEST_EA(env, insn, OS_LONG, dest, &addr);
} else {
SRC_EA(src, OS_LONG, 0, NULL);
SRC_EA(env, src, OS_LONG, 0, NULL);
tcg_gen_or_i32(dest, src, reg);
tcg_gen_mov_i32(reg, dest);
}
@ -1725,7 +1735,7 @@ DISAS_INSN(suba)
TCGv src;
TCGv reg;
SRC_EA(src, OS_LONG, 0, NULL);
SRC_EA(env, src, OS_LONG, 0, NULL);
reg = AREG(insn, 9);
tcg_gen_sub_i32(reg, reg, src);
}
@ -1751,7 +1761,7 @@ DISAS_INSN(mov3q)
val = -1;
src = tcg_const_i32(val);
gen_logic_cc(s, src);
DEST_EA(insn, OS_LONG, src, NULL);
DEST_EA(env, insn, OS_LONG, src, NULL);
}
DISAS_INSN(cmp)
@ -1779,7 +1789,7 @@ DISAS_INSN(cmp)
default:
abort();
}
SRC_EA(src, opsize, 1, NULL);
SRC_EA(env, src, opsize, 1, NULL);
reg = DREG(insn, 9);
dest = tcg_temp_new();
tcg_gen_sub_i32(dest, reg, src);
@ -1798,7 +1808,7 @@ DISAS_INSN(cmpa)
} else {
opsize = OS_WORD;
}
SRC_EA(src, opsize, 1, NULL);
SRC_EA(env, src, opsize, 1, NULL);
reg = AREG(insn, 9);
dest = tcg_temp_new();
tcg_gen_sub_i32(dest, reg, src);
@ -1813,12 +1823,12 @@ DISAS_INSN(eor)
TCGv dest;
TCGv addr;
SRC_EA(src, OS_LONG, 0, &addr);
SRC_EA(env, src, OS_LONG, 0, &addr);
reg = DREG(insn, 9);
dest = tcg_temp_new();
tcg_gen_xor_i32(dest, src, reg);
gen_logic_cc(s, dest);
DEST_EA(insn, OS_LONG, dest, &addr);
DEST_EA(env, insn, OS_LONG, dest, &addr);
}
DISAS_INSN(and)
@ -1831,11 +1841,11 @@ DISAS_INSN(and)
reg = DREG(insn, 9);
dest = tcg_temp_new();
if (insn & 0x100) {
SRC_EA(src, OS_LONG, 0, &addr);
SRC_EA(env, src, OS_LONG, 0, &addr);
tcg_gen_and_i32(dest, src, reg);
DEST_EA(insn, OS_LONG, dest, &addr);
DEST_EA(env, insn, OS_LONG, dest, &addr);
} else {
SRC_EA(src, OS_LONG, 0, NULL);
SRC_EA(env, src, OS_LONG, 0, NULL);
tcg_gen_and_i32(dest, src, reg);
tcg_gen_mov_i32(reg, dest);
}
@ -1847,7 +1857,7 @@ DISAS_INSN(adda)
TCGv src;
TCGv reg;
SRC_EA(src, OS_LONG, 0, NULL);
SRC_EA(env, src, OS_LONG, 0, NULL);
reg = AREG(insn, 9);
tcg_gen_add_i32(reg, reg, src);
}
@ -1936,13 +1946,13 @@ DISAS_INSN(strldsr)
uint32_t addr;
addr = s->pc - 2;
ext = cpu_lduw_code(cpu_single_env, s->pc);
ext = cpu_lduw_code(env, s->pc);
s->pc += 2;
if (ext != 0x46FC) {
gen_exception(s, addr, EXCP_UNSUPPORTED);
return;
}
ext = cpu_lduw_code(cpu_single_env, s->pc);
ext = cpu_lduw_code(env, s->pc);
s->pc += 2;
if (IS_USER(s) || (ext & SR_S) == 0) {
gen_exception(s, addr, EXCP_PRIVILEGE);
@ -1972,7 +1982,7 @@ DISAS_INSN(move_to_sr)
gen_exception(s, s->pc - 2, EXCP_PRIVILEGE);
return;
}
gen_set_sr(s, insn, 0);
gen_set_sr(env, s, insn, 0);
gen_lookup_tb(s);
}
@ -2010,7 +2020,7 @@ DISAS_INSN(stop)
return;
}
ext = cpu_lduw_code(cpu_single_env, s->pc);
ext = cpu_lduw_code(env, s->pc);
s->pc += 2;
gen_set_sr_im(s, ext, 0);
@ -2037,7 +2047,7 @@ DISAS_INSN(movec)
return;
}
ext = cpu_lduw_code(cpu_single_env, s->pc);
ext = cpu_lduw_code(env, s->pc);
s->pc += 2;
if (ext & 0x8000) {
@ -2102,7 +2112,7 @@ DISAS_INSN(fpu)
int set_dest;
int opsize;
ext = cpu_lduw_code(cpu_single_env, s->pc);
ext = cpu_lduw_code(env, s->pc);
s->pc += 2;
opmode = ext & 0x7f;
switch ((ext >> 13) & 7) {
@ -2138,7 +2148,7 @@ DISAS_INSN(fpu)
tcg_gen_addi_i32(tmp32, tmp32, -8);
break;
case 5:
offset = cpu_ldsw_code(cpu_single_env, s->pc);
offset = cpu_ldsw_code(env, s->pc);
s->pc += 2;
tcg_gen_addi_i32(tmp32, tmp32, offset);
break;
@ -2164,7 +2174,7 @@ DISAS_INSN(fpu)
default:
goto undef;
}
DEST_EA(insn, opsize, tmp32, NULL);
DEST_EA(env, insn, opsize, tmp32, NULL);
tcg_temp_free_i32(tmp32);
return;
case 4: /* fmove to control register. */
@ -2192,7 +2202,7 @@ DISAS_INSN(fpu)
(ext >> 10) & 7);
goto undef;
}
DEST_EA(insn, OS_LONG, tmp32, NULL);
DEST_EA(env, insn, OS_LONG, tmp32, NULL);
break;
case 6: /* fmovem */
case 7:
@ -2202,7 +2212,7 @@ DISAS_INSN(fpu)
int i;
if ((ext & 0x1f00) != 0x1000 || (ext & 0xff) == 0)
goto undef;
tmp32 = gen_lea(s, insn, OS_LONG);
tmp32 = gen_lea(env, s, insn, OS_LONG);
if (IS_NULL_QREG(tmp32)) {
gen_addr_fault(s);
return;
@ -2252,12 +2262,12 @@ DISAS_INSN(fpu)
tcg_gen_addi_i32(tmp32, tmp32, -8);
break;
case 5:
offset = cpu_ldsw_code(cpu_single_env, s->pc);
offset = cpu_ldsw_code(env, s->pc);
s->pc += 2;
tcg_gen_addi_i32(tmp32, tmp32, offset);
break;
case 7:
offset = cpu_ldsw_code(cpu_single_env, s->pc);
offset = cpu_ldsw_code(env, s->pc);
offset += s->pc - 2;
s->pc += 2;
tcg_gen_addi_i32(tmp32, tmp32, offset);
@ -2277,7 +2287,7 @@ DISAS_INSN(fpu)
}
tcg_temp_free_i32(tmp32);
} else {
SRC_EA(tmp32, opsize, 1, NULL);
SRC_EA(env, tmp32, opsize, 1, NULL);
src = tcg_temp_new_i64();
switch (opsize) {
case OS_LONG:
@ -2372,7 +2382,7 @@ DISAS_INSN(fpu)
undef:
/* FIXME: Is this right for offset addressing modes? */
s->pc -= 2;
disas_undef_fpu(s, insn);
disas_undef_fpu(env, s, insn);
}
DISAS_INSN(fbcc)
@ -2383,10 +2393,10 @@ DISAS_INSN(fbcc)
int l1;
addr = s->pc;
offset = cpu_ldsw_code(cpu_single_env, s->pc);
offset = cpu_ldsw_code(env, s->pc);
s->pc += 2;
if (insn & (1 << 6)) {
offset = (offset << 16) | cpu_lduw_code(cpu_single_env, s->pc);
offset = (offset << 16) | cpu_lduw_code(env, s->pc);
s->pc += 2;
}
@ -2508,18 +2518,18 @@ DISAS_INSN(mac)
s->done_mac = 1;
}
ext = cpu_lduw_code(cpu_single_env, s->pc);
ext = cpu_lduw_code(env, s->pc);
s->pc += 2;
acc = ((insn >> 7) & 1) | ((ext >> 3) & 2);
dual = ((insn & 0x30) != 0 && (ext & 3) != 0);
if (dual && !m68k_feature(s->env, M68K_FEATURE_CF_EMAC_B)) {
disas_undef(s, insn);
disas_undef(env, s, insn);
return;
}
if (insn & 0x30) {
/* MAC with load. */
tmp = gen_lea(s, insn, OS_LONG);
tmp = gen_lea(env, s, insn, OS_LONG);
addr = tcg_temp_new();
tcg_gen_and_i32(addr, tmp, QREG_MAC_MASK);
/* Load the value now to ensure correct exception behavior.
@ -2733,7 +2743,7 @@ DISAS_INSN(to_mac)
int accnum;
accnum = (insn >> 9) & 3;
acc = MACREG(accnum);
SRC_EA(val, OS_LONG, 0, NULL);
SRC_EA(env, val, OS_LONG, 0, NULL);
if (s->env->macsr & MACSR_FI) {
tcg_gen_ext_i32_i64(acc, val);
tcg_gen_shli_i64(acc, acc, 8);
@ -2750,7 +2760,7 @@ DISAS_INSN(to_mac)
DISAS_INSN(to_macsr)
{
TCGv val;
SRC_EA(val, OS_LONG, 0, NULL);
SRC_EA(env, val, OS_LONG, 0, NULL);
gen_helper_set_macsr(cpu_env, val);
gen_lookup_tb(s);
}
@ -2758,7 +2768,7 @@ DISAS_INSN(to_macsr)
DISAS_INSN(to_mask)
{
TCGv val;
SRC_EA(val, OS_LONG, 0, NULL);
SRC_EA(env, val, OS_LONG, 0, NULL);
tcg_gen_ori_i32(QREG_MAC_MASK, val, 0xffff0000);
}
@ -2766,7 +2776,7 @@ DISAS_INSN(to_mext)
{
TCGv val;
TCGv acc;
SRC_EA(val, OS_LONG, 0, NULL);
SRC_EA(env, val, OS_LONG, 0, NULL);
acc = tcg_const_i32((insn & 0x400) ? 2 : 0);
if (s->env->macsr & MACSR_FI)
gen_helper_set_mac_extf(cpu_env, val, acc);
@ -2943,10 +2953,10 @@ static void disas_m68k_insn(CPUM68KState * env, DisasContext *s)
{
uint16_t insn;
insn = cpu_lduw_code(cpu_single_env, s->pc);
insn = cpu_lduw_code(env, s->pc);
s->pc += 2;
opcode_table[insn](s, insn);
opcode_table[insn](env, s, insn);
}
/* generate intermediate code for basic block 'tb'. */