RISC-V: Adding T-Head FMemIdx extension
This patch adds support for the T-Head FMemIdx instructions. The patch uses the T-Head specific decoder and translation. Co-developed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu> Message-Id: <20230131202013.2541053-11-christoph.muellner@vrull.eu> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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@ -114,6 +114,7 @@ static const struct isa_ext_data isa_edata_arr[] = {
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ISA_EXT_DATA_ENTRY(xtheadbs, true, PRIV_VERSION_1_11_0, ext_xtheadbs),
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ISA_EXT_DATA_ENTRY(xtheadcmo, true, PRIV_VERSION_1_11_0, ext_xtheadcmo),
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ISA_EXT_DATA_ENTRY(xtheadcondmov, true, PRIV_VERSION_1_11_0, ext_xtheadcondmov),
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ISA_EXT_DATA_ENTRY(xtheadfmemidx, true, PRIV_VERSION_1_11_0, ext_xtheadfmemidx),
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ISA_EXT_DATA_ENTRY(xtheadmac, true, PRIV_VERSION_1_11_0, ext_xtheadmac),
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ISA_EXT_DATA_ENTRY(xtheadmemidx, true, PRIV_VERSION_1_11_0, ext_xtheadmemidx),
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ISA_EXT_DATA_ENTRY(xtheadmempair, true, PRIV_VERSION_1_11_0, ext_xtheadmempair),
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@ -1102,6 +1103,7 @@ static Property riscv_cpu_extensions[] = {
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DEFINE_PROP_BOOL("xtheadbs", RISCVCPU, cfg.ext_xtheadbs, false),
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DEFINE_PROP_BOOL("xtheadcmo", RISCVCPU, cfg.ext_xtheadcmo, false),
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DEFINE_PROP_BOOL("xtheadcondmov", RISCVCPU, cfg.ext_xtheadcondmov, false),
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DEFINE_PROP_BOOL("xtheadfmemidx", RISCVCPU, cfg.ext_xtheadfmemidx, false),
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DEFINE_PROP_BOOL("xtheadmac", RISCVCPU, cfg.ext_xtheadmac, false),
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DEFINE_PROP_BOOL("xtheadmemidx", RISCVCPU, cfg.ext_xtheadmemidx, false),
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DEFINE_PROP_BOOL("xtheadmempair", RISCVCPU, cfg.ext_xtheadmempair, false),
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@ -478,6 +478,7 @@ struct RISCVCPUConfig {
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bool ext_xtheadbs;
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bool ext_xtheadcmo;
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bool ext_xtheadcondmov;
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bool ext_xtheadfmemidx;
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bool ext_xtheadmac;
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bool ext_xtheadmemidx;
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bool ext_xtheadmempair;
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@ -46,6 +46,12 @@
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} \
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} while (0)
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#define REQUIRE_XTHEADFMEMIDX(ctx) do { \
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if (!ctx->cfg_ptr->ext_xtheadfmemidx) { \
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return false; \
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} \
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} while (0)
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#define REQUIRE_XTHEADMAC(ctx) do { \
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if (!ctx->cfg_ptr->ext_xtheadmac) { \
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return false; \
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@ -341,6 +347,108 @@ static bool trans_th_mvnez(DisasContext *ctx, arg_th_mveqz *a)
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return gen_th_condmove(ctx, a, TCG_COND_NE);
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}
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/* XTheadFMem */
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/*
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* Load 64-bit float from indexed address.
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* If !zext_offs, then address is rs1 + (rs2 << imm2).
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* If zext_offs, then address is rs1 + (zext(rs2[31:0]) << imm2).
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*/
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static bool gen_fload_idx(DisasContext *ctx, arg_th_memidx *a, MemOp memop,
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bool zext_offs)
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{
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TCGv_i64 rd = cpu_fpr[a->rd];
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TCGv addr = get_th_address_indexed(ctx, a->rs1, a->rs2, a->imm2, zext_offs);
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tcg_gen_qemu_ld_i64(rd, addr, ctx->mem_idx, memop);
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if ((memop & MO_SIZE) == MO_32) {
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gen_nanbox_s(rd, rd);
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}
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mark_fs_dirty(ctx);
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return true;
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}
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/*
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* Store 64-bit float to indexed address.
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* If !zext_offs, then address is rs1 + (rs2 << imm2).
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* If zext_offs, then address is rs1 + (zext(rs2[31:0]) << imm2).
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*/
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static bool gen_fstore_idx(DisasContext *ctx, arg_th_memidx *a, MemOp memop,
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bool zext_offs)
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{
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TCGv_i64 rd = cpu_fpr[a->rd];
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TCGv addr = get_th_address_indexed(ctx, a->rs1, a->rs2, a->imm2, zext_offs);
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tcg_gen_qemu_st_i64(rd, addr, ctx->mem_idx, memop);
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return true;
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}
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static bool trans_th_flrd(DisasContext *ctx, arg_th_memidx *a)
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{
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REQUIRE_XTHEADFMEMIDX(ctx);
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REQUIRE_FPU;
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REQUIRE_EXT(ctx, RVD);
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return gen_fload_idx(ctx, a, MO_TEUQ, false);
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}
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static bool trans_th_flrw(DisasContext *ctx, arg_th_memidx *a)
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{
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REQUIRE_XTHEADFMEMIDX(ctx);
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REQUIRE_FPU;
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REQUIRE_EXT(ctx, RVF);
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return gen_fload_idx(ctx, a, MO_TEUL, false);
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}
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static bool trans_th_flurd(DisasContext *ctx, arg_th_memidx *a)
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{
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REQUIRE_XTHEADFMEMIDX(ctx);
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REQUIRE_FPU;
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REQUIRE_EXT(ctx, RVD);
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return gen_fload_idx(ctx, a, MO_TEUQ, true);
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}
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static bool trans_th_flurw(DisasContext *ctx, arg_th_memidx *a)
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{
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REQUIRE_XTHEADFMEMIDX(ctx);
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REQUIRE_FPU;
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REQUIRE_EXT(ctx, RVF);
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return gen_fload_idx(ctx, a, MO_TEUL, true);
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}
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static bool trans_th_fsrd(DisasContext *ctx, arg_th_memidx *a)
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{
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REQUIRE_XTHEADFMEMIDX(ctx);
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REQUIRE_FPU;
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REQUIRE_EXT(ctx, RVD);
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return gen_fstore_idx(ctx, a, MO_TEUQ, false);
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}
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static bool trans_th_fsrw(DisasContext *ctx, arg_th_memidx *a)
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{
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REQUIRE_XTHEADFMEMIDX(ctx);
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REQUIRE_FPU;
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REQUIRE_EXT(ctx, RVF);
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return gen_fstore_idx(ctx, a, MO_TEUL, false);
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}
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static bool trans_th_fsurd(DisasContext *ctx, arg_th_memidx *a)
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{
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REQUIRE_XTHEADFMEMIDX(ctx);
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REQUIRE_FPU;
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REQUIRE_EXT(ctx, RVD);
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return gen_fstore_idx(ctx, a, MO_TEUQ, true);
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}
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static bool trans_th_fsurw(DisasContext *ctx, arg_th_memidx *a)
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{
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REQUIRE_XTHEADFMEMIDX(ctx);
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REQUIRE_FPU;
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REQUIRE_EXT(ctx, RVF);
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return gen_fstore_idx(ctx, a, MO_TEUL, true);
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}
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/* XTheadMac */
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static bool gen_th_mac(DisasContext *ctx, arg_r *a,
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@ -134,7 +134,8 @@ static bool has_xthead_p(DisasContext *ctx __attribute__((__unused__)))
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{
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return ctx->cfg_ptr->ext_xtheadba || ctx->cfg_ptr->ext_xtheadbb ||
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ctx->cfg_ptr->ext_xtheadbs || ctx->cfg_ptr->ext_xtheadcmo ||
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ctx->cfg_ptr->ext_xtheadcondmov || ctx->cfg_ptr->ext_xtheadmac ||
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ctx->cfg_ptr->ext_xtheadcondmov ||
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ctx->cfg_ptr->ext_xtheadfmemidx || ctx->cfg_ptr->ext_xtheadmac ||
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ctx->cfg_ptr->ext_xtheadmemidx || ctx->cfg_ptr->ext_xtheadmempair ||
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ctx->cfg_ptr->ext_xtheadsync;
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}
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@ -100,6 +100,16 @@ th_l2cache_iall 0000000 10110 00000 000 00000 0001011
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th_mveqz 0100000 ..... ..... 001 ..... 0001011 @r
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th_mvnez 0100001 ..... ..... 001 ..... 0001011 @r
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# XTheadFMemIdx
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th_flrd 01100 .. ..... ..... 110 ..... 0001011 @th_memidx
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th_flrw 01000 .. ..... ..... 110 ..... 0001011 @th_memidx
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th_flurd 01110 .. ..... ..... 110 ..... 0001011 @th_memidx
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th_flurw 01010 .. ..... ..... 110 ..... 0001011 @th_memidx
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th_fsrd 01100 .. ..... ..... 111 ..... 0001011 @th_memidx
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th_fsrw 01000 .. ..... ..... 111 ..... 0001011 @th_memidx
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th_fsurd 01110 .. ..... ..... 111 ..... 0001011 @th_memidx
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th_fsurw 01010 .. ..... ..... 111 ..... 0001011 @th_memidx
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# XTheadMac
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th_mula 00100 00 ..... ..... 001 ..... 0001011 @r
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th_mulah 00101 00 ..... ..... 001 ..... 0001011 @r
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