i.MX: Add i2C devices to i.MX31 SOC
Signed-off-by: Jean-Christophe Dubois <jcd@tribudubois.net> Reviewed-by: Peter Crosthwaite <crosthwaite.peter@gmail.com> Message-id: fb20e6bf5cf946c4530b2cfb55c7e37f5a0fc051.1441057361.git.jcd@tribudubois.net Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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@ -50,6 +50,11 @@ static void fsl_imx31_init(Object *obj)
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object_initialize(&s->epit[i], sizeof(s->epit[i]), TYPE_IMX_EPIT);
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qdev_set_parent_bus(DEVICE(&s->epit[i]), sysbus_get_default());
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}
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for (i = 0; i < FSL_IMX31_NUM_I2CS; i++) {
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object_initialize(&s->i2c[i], sizeof(s->i2c[i]), TYPE_IMX_I2C);
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qdev_set_parent_bus(DEVICE(&s->i2c[i]), sysbus_get_default());
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}
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}
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static void fsl_imx31_realize(DeviceState *dev, Error **errp)
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@ -154,6 +159,31 @@ static void fsl_imx31_realize(DeviceState *dev, Error **errp)
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epit_table[i].irq));
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}
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/* Initialize all I2C */
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for (i = 0; i < FSL_IMX31_NUM_I2CS; i++) {
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static const struct {
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hwaddr addr;
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unsigned int irq;
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} i2c_table[FSL_IMX31_NUM_I2CS] = {
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{ FSL_IMX31_I2C1_ADDR, FSL_IMX31_I2C1_IRQ },
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{ FSL_IMX31_I2C2_ADDR, FSL_IMX31_I2C2_IRQ },
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{ FSL_IMX31_I2C3_ADDR, FSL_IMX31_I2C3_IRQ }
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};
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/* Initialize the I2C */
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object_property_set_bool(OBJECT(&s->i2c[i]), true, "realized", &err);
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if (err) {
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error_propagate(errp, err);
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return;
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}
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/* Map I2C memory */
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sysbus_mmio_map(SYS_BUS_DEVICE(&s->i2c[i]), 0, i2c_table[i].addr);
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/* Connect I2C IRQ to PIC */
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sysbus_connect_irq(SYS_BUS_DEVICE(&s->i2c[i]), 0,
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qdev_get_gpio_in(DEVICE(&s->avic),
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i2c_table[i].irq));
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}
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/* On a real system, the first 16k is a `secure boot rom' */
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memory_region_init_rom_device(&s->secure_rom, NULL, NULL, NULL,
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"imx31.secure_rom",
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@ -31,6 +31,7 @@
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#define FSL_IMX31_NUM_UARTS 2
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#define FSL_IMX31_NUM_EPITS 2
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#define FSL_IMX31_NUM_I2CS 3
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typedef struct FslIMX31State {
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/*< private >*/
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@ -43,6 +44,7 @@ typedef struct FslIMX31State {
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IMXSerialState uart[FSL_IMX31_NUM_UARTS];
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IMXGPTState gpt;
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IMXEPITState epit[FSL_IMX31_NUM_EPITS];
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IMXI2CState i2c[FSL_IMX31_NUM_I2CS];
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MemoryRegion secure_rom;
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MemoryRegion rom;
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MemoryRegion iram;
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@ -57,10 +59,16 @@ typedef struct FslIMX31State {
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#define FSL_IMX31_IRAM_ALIAS_SIZE 0xFFC0000
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#define FSL_IMX31_IRAM_ADDR 0x1FFFC000
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#define FSL_IMX31_IRAM_SIZE 0x4000
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#define FSL_IMX31_I2C1_ADDR 0x43F80000
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#define FSL_IMX31_I2C1_SIZE 0x4000
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#define FSL_IMX31_I2C3_ADDR 0x43F84000
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#define FSL_IMX31_I2C3_SIZE 0x4000
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#define FSL_IMX31_UART1_ADDR 0x43F90000
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#define FSL_IMX31_UART1_SIZE 0x4000
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#define FSL_IMX31_UART2_ADDR 0x43F94000
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#define FSL_IMX31_UART2_SIZE 0x4000
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#define FSL_IMX31_I2C2_ADDR 0x43F98000
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#define FSL_IMX31_I2C2_SIZE 0x4000
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#define FSL_IMX31_CCM_ADDR 0x53F80000
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#define FSL_IMX31_CCM_SIZE 0x4000
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#define FSL_IMX31_GPT_ADDR 0x53F90000
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@ -95,5 +103,8 @@ typedef struct FslIMX31State {
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#define FSL_IMX31_GPT_IRQ 29
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#define FSL_IMX31_UART2_IRQ 32
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#define FSL_IMX31_UART1_IRQ 45
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#define FSL_IMX31_I2C1_IRQ 10
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#define FSL_IMX31_I2C2_IRQ 4
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#define FSL_IMX31_I2C3_IRQ 3
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#endif /* FSL_IMX31_H */
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