hw/arm/virt-acpi-build: Add PCIe controller in ACPI DSDT table
Add PCIe controller in ACPI DSDT table, so the guest can detect the PCIe. Signed-off-by: Shannon Zhao <zhaoshenglong@huawei.com> Signed-off-by: Shannon Zhao <shannon.zhao@linaro.org> Message-id: 1432522520-8068-23-git-send-email-zhaoshenglong@huawei.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Shannon Zhao
Peter Maydell
parent
e1f776c434
commit
d4e5de1ae0
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@ -40,6 +40,7 @@
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#include "hw/hw.h"
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#include "hw/acpi/aml-build.h"
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#include "hw/pci/pcie_host.h"
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#include "hw/pci/pci.h"
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#define ARM_SPI_BASE 32
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@ -152,6 +153,157 @@ static void acpi_dsdt_add_virtio(Aml *scope,
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}
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}
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static void acpi_dsdt_add_pci(Aml *scope, const MemMapEntry *memmap, int irq)
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{
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Aml *method, *crs, *ifctx, *UUID, *ifctx1, *elsectx, *buf;
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int i, bus_no;
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hwaddr base_mmio = memmap[VIRT_PCIE_MMIO].base;
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hwaddr size_mmio = memmap[VIRT_PCIE_MMIO].size;
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hwaddr base_pio = memmap[VIRT_PCIE_PIO].base;
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hwaddr size_pio = memmap[VIRT_PCIE_PIO].size;
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hwaddr base_ecam = memmap[VIRT_PCIE_ECAM].base;
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hwaddr size_ecam = memmap[VIRT_PCIE_ECAM].size;
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int nr_pcie_buses = size_ecam / PCIE_MMCFG_SIZE_MIN;
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Aml *dev = aml_device("%s", "PCI0");
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aml_append(dev, aml_name_decl("_HID", aml_string("PNP0A08")));
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aml_append(dev, aml_name_decl("_CID", aml_string("PNP0A03")));
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aml_append(dev, aml_name_decl("_SEG", aml_int(0)));
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aml_append(dev, aml_name_decl("_BBN", aml_int(0)));
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aml_append(dev, aml_name_decl("_ADR", aml_int(0)));
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aml_append(dev, aml_name_decl("_UID", aml_string("PCI0")));
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aml_append(dev, aml_name_decl("_STR", aml_unicode("PCIe 0 Device")));
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/* Declare the PCI Routing Table. */
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Aml *rt_pkg = aml_package(nr_pcie_buses * PCI_NUM_PINS);
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for (bus_no = 0; bus_no < nr_pcie_buses; bus_no++) {
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for (i = 0; i < PCI_NUM_PINS; i++) {
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int gsi = (i + bus_no) % PCI_NUM_PINS;
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Aml *pkg = aml_package(4);
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aml_append(pkg, aml_int((bus_no << 16) | 0xFFFF));
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aml_append(pkg, aml_int(i));
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aml_append(pkg, aml_name("GSI%d", gsi));
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aml_append(pkg, aml_int(0));
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aml_append(rt_pkg, pkg);
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}
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}
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aml_append(dev, aml_name_decl("_PRT", rt_pkg));
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/* Create GSI link device */
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for (i = 0; i < PCI_NUM_PINS; i++) {
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Aml *dev_gsi = aml_device("GSI%d", i);
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aml_append(dev_gsi, aml_name_decl("_HID", aml_string("PNP0C0F")));
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aml_append(dev_gsi, aml_name_decl("_UID", aml_int(0)));
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crs = aml_resource_template();
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aml_append(crs,
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aml_interrupt(AML_CONSUMER, AML_LEVEL, AML_ACTIVE_HIGH,
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AML_EXCLUSIVE, irq + i));
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aml_append(dev_gsi, aml_name_decl("_PRS", crs));
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crs = aml_resource_template();
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aml_append(crs,
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aml_interrupt(AML_CONSUMER, AML_LEVEL, AML_ACTIVE_HIGH,
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AML_EXCLUSIVE, irq + i));
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aml_append(dev_gsi, aml_name_decl("_CRS", crs));
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method = aml_method("_SRS", 1);
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aml_append(dev_gsi, method);
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aml_append(dev, dev_gsi);
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}
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method = aml_method("_CBA", 0);
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aml_append(method, aml_return(aml_int(base_ecam)));
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aml_append(dev, method);
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method = aml_method("_CRS", 0);
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Aml *rbuf = aml_resource_template();
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aml_append(rbuf,
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aml_word_bus_number(AML_MIN_FIXED, AML_MAX_FIXED, AML_POS_DECODE,
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0x0000, 0x0000, nr_pcie_buses - 1, 0x0000,
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nr_pcie_buses));
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aml_append(rbuf,
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aml_dword_memory(AML_POS_DECODE, AML_MIN_FIXED, AML_MAX_FIXED,
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AML_NON_CACHEABLE, AML_READ_WRITE, 0x0000, base_mmio,
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base_mmio + size_mmio - 1, 0x0000, size_mmio));
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aml_append(rbuf,
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aml_dword_io(AML_MIN_FIXED, AML_MAX_FIXED, AML_POS_DECODE,
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AML_ENTIRE_RANGE, 0x0000, 0x0000, size_pio - 1, base_pio,
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size_pio));
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aml_append(method, aml_name_decl("RBUF", rbuf));
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aml_append(method, aml_return(rbuf));
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aml_append(dev, method);
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/* Declare an _OSC (OS Control Handoff) method */
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aml_append(dev, aml_name_decl("SUPP", aml_int(0)));
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aml_append(dev, aml_name_decl("CTRL", aml_int(0)));
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method = aml_method("_OSC", 4);
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aml_append(method,
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aml_create_dword_field(aml_arg(3), aml_int(0), "CDW1"));
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/* PCI Firmware Specification 3.0
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* 4.5.1. _OSC Interface for PCI Host Bridge Devices
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* The _OSC interface for a PCI/PCI-X/PCI Express hierarchy is
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* identified by the Universal Unique IDentifier (UUID)
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* 33DB4D5B-1FF7-401C-9657-7441C03DD766
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*/
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UUID = aml_touuid("33DB4D5B-1FF7-401C-9657-7441C03DD766");
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ifctx = aml_if(aml_equal(aml_arg(0), UUID));
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aml_append(ifctx,
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aml_create_dword_field(aml_arg(3), aml_int(4), "CDW2"));
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aml_append(ifctx,
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aml_create_dword_field(aml_arg(3), aml_int(8), "CDW3"));
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aml_append(ifctx, aml_store(aml_name("CDW2"), aml_name("SUPP")));
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aml_append(ifctx, aml_store(aml_name("CDW3"), aml_name("CTRL")));
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aml_append(ifctx, aml_store(aml_and(aml_name("CTRL"), aml_int(0x1D)),
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aml_name("CTRL")));
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ifctx1 = aml_if(aml_lnot(aml_equal(aml_arg(1), aml_int(0x1))));
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aml_append(ifctx1, aml_store(aml_or(aml_name("CDW1"), aml_int(0x08)),
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aml_name("CDW1")));
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aml_append(ifctx, ifctx1);
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ifctx1 = aml_if(aml_lnot(aml_equal(aml_name("CDW3"), aml_name("CTRL"))));
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aml_append(ifctx1, aml_store(aml_or(aml_name("CDW1"), aml_int(0x10)),
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aml_name("CDW1")));
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aml_append(ifctx, ifctx1);
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aml_append(ifctx, aml_store(aml_name("CTRL"), aml_name("CDW3")));
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aml_append(ifctx, aml_return(aml_arg(3)));
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aml_append(method, ifctx);
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elsectx = aml_else();
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aml_append(elsectx, aml_store(aml_or(aml_name("CDW1"), aml_int(4)),
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aml_name("CDW1")));
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aml_append(elsectx, aml_return(aml_arg(3)));
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aml_append(method, elsectx);
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aml_append(dev, method);
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method = aml_method("_DSM", 4);
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/* PCI Firmware Specification 3.0
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* 4.6.1. _DSM for PCI Express Slot Information
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* The UUID in _DSM in this context is
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* {E5C937D0-3553-4D7A-9117-EA4D19C3434D}
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*/
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UUID = aml_touuid("E5C937D0-3553-4D7A-9117-EA4D19C3434D");
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ifctx = aml_if(aml_equal(aml_arg(0), UUID));
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ifctx1 = aml_if(aml_equal(aml_arg(2), aml_int(0)));
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uint8_t byte_list[1] = {1};
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buf = aml_buffer(1, byte_list);
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aml_append(ifctx1, aml_return(buf));
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aml_append(ifctx, ifctx1);
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aml_append(method, ifctx);
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byte_list[0] = 0;
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buf = aml_buffer(1, byte_list);
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aml_append(method, aml_return(buf));
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aml_append(dev, method);
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Aml *dev_rp0 = aml_device("%s", "RP0");
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aml_append(dev_rp0, aml_name_decl("_ADR", aml_int(0)));
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aml_append(dev, dev_rp0);
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aml_append(scope, dev);
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}
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/* RSDP */
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static GArray *
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build_rsdp(GArray *rsdp_table, GArray *linker, unsigned rsdt)
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@ -309,6 +461,8 @@ build_dsdt(GArray *table_data, GArray *linker, VirtGuestInfo *guest_info)
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acpi_dsdt_add_flash(scope, &memmap[VIRT_FLASH]);
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acpi_dsdt_add_virtio(scope, &memmap[VIRT_MMIO],
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(irqmap[VIRT_MMIO] + ARM_SPI_BASE), NUM_VIRTIO_TRANSPORTS);
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acpi_dsdt_add_pci(scope, memmap, (irqmap[VIRT_PCIE] + ARM_SPI_BASE));
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aml_append(dsdt, scope);
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/* copy AML table into ACPI tables blob and patch header there */
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