OpenE2K/qemu-e2k
13
4
Fork 0
Code Issues 4 Pull Requests Projects 2 Releases Activity

target/arm: Report M-profile alignment faults correctly to the guest

Browse Source 
For M-profile, we weren't reporting alignment faults triggered by the
generic TCG code correctly to the guest.  These get passed into
arm_v7m_cpu_do_interrupt() as an EXCP_DATA_ABORT with an A-profile
style exception.fsr value of 1.  We didn't check for this, and so
they fell through into the default of "assume this is an MPU fault"
and were reported to the guest as a data access violation MPU fault.

Report these alignment faults as UsageFaults which set the UNALIGNED
bit in the UFSR.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210723162146.5167-4-peter.maydell@linaro.org
This commit is contained in:
Peter Maydell 2021-07-23 17:21:43 +01:00
parent 0c317eb3dd
commit d4f6883912
1 changed files with 8 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

8
target/arm/m_helper.c
View File

@ -2248,6 +2248,7 @@ void arm_v7m_cpu_do_interrupt(CPUState *cs)
env->v7m.sfsr |= R_V7M_SFSR_LSERR_MASK;
break;
case EXCP_UNALIGNED:
/* Unaligned faults reported by M-profile aware code */
armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_USAGE, env->v7m.secure);
env->v7m.cfsr[env->v7m.secure] |= R_V7M_CFSR_UNALIGNED_MASK;
break;
@ -2320,6 +2321,13 @@ void arm_v7m_cpu_do_interrupt(CPUState *cs)
}
armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_BUS, false);
break;
case 0x1: /* Alignment fault reported by generic code */
qemu_log_mask(CPU_LOG_INT,
"...really UsageFault with UFSR.UNALIGNED\n");
env->v7m.cfsr[env->v7m.secure] |= R_V7M_CFSR_UNALIGNED_MASK;
armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_USAGE,
env->v7m.secure);
break;
default:
/*
* All other FSR values are either MPU faults or "can't happen