accel/tcg: Add 'size' param to probe_access_full
Change to match the recent change to probe_access_flags. All existing callers updated to supply 0, so no change in behaviour. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
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@ -1589,12 +1589,12 @@ static int probe_access_internal(CPUArchState *env, target_ulong addr,
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return flags;
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}
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int probe_access_full(CPUArchState *env, target_ulong addr,
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int probe_access_full(CPUArchState *env, target_ulong addr, int size,
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MMUAccessType access_type, int mmu_idx,
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bool nonfault, void **phost, CPUTLBEntryFull **pfull,
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uintptr_t retaddr)
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{
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int flags = probe_access_internal(env, addr, 0, access_type, mmu_idx,
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int flags = probe_access_internal(env, addr, size, access_type, mmu_idx,
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nonfault, phost, pfull, retaddr);
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/* Handle clean RAM pages. */
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@ -475,7 +475,7 @@ int probe_access_flags(CPUArchState *env, target_ulong addr, int size,
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* and must be consumed or copied immediately, before any further
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* access or changes to TLB @mmu_idx.
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*/
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int probe_access_full(CPUArchState *env, target_ulong addr,
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int probe_access_full(CPUArchState *env, target_ulong addr, int size,
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MMUAccessType access_type, int mmu_idx,
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bool nonfault, void **phost,
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CPUTLBEntryFull **pfull, uintptr_t retaddr);
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@ -259,7 +259,7 @@ static bool S1_ptw_translate(CPUARMState *env, S1Translate *ptw,
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int flags;
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env->tlb_fi = fi;
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flags = probe_access_full(env, addr, MMU_DATA_LOAD,
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flags = probe_access_full(env, addr, 0, MMU_DATA_LOAD,
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arm_to_core_mmu_idx(s2_mmu_idx),
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true, &ptw->out_host, &full, 0);
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env->tlb_fi = NULL;
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@ -118,7 +118,7 @@ static uint8_t *allocation_tag_mem(CPUARMState *env, int ptr_mmu_idx,
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* valid. Indicate to probe_access_flags no-fault, then assert that
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* we received a valid page.
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*/
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flags = probe_access_full(env, ptr, ptr_access, ptr_mmu_idx,
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flags = probe_access_full(env, ptr, 0, ptr_access, ptr_mmu_idx,
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ra == 0, &host, &full, ra);
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assert(!(flags & TLB_INVALID_MASK));
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@ -154,7 +154,7 @@ static uint8_t *allocation_tag_mem(CPUARMState *env, int ptr_mmu_idx,
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*/
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in_page = -(ptr | TARGET_PAGE_MASK);
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if (unlikely(ptr_size > in_page)) {
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flags |= probe_access_full(env, ptr + in_page, ptr_access,
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flags |= probe_access_full(env, ptr + in_page, 0, ptr_access,
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ptr_mmu_idx, ra == 0, &host, &full, ra);
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assert(!(flags & TLB_INVALID_MASK));
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}
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@ -5356,7 +5356,7 @@ bool sve_probe_page(SVEHostPage *info, bool nofault, CPUARMState *env,
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&info->host, retaddr);
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#else
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CPUTLBEntryFull *full;
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flags = probe_access_full(env, addr, access_type, mmu_idx, nofault,
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flags = probe_access_full(env, addr, 0, access_type, mmu_idx, nofault,
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&info->host, &full, retaddr);
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#endif
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info->flags = flags;
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@ -14651,7 +14651,7 @@ static bool is_guarded_page(CPUARMState *env, DisasContext *s)
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* that the TLB entry must be present and valid, and thus this
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* access will never raise an exception.
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*/
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flags = probe_access_full(env, addr, MMU_INST_FETCH, mmu_idx,
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flags = probe_access_full(env, addr, 0, MMU_INST_FETCH, mmu_idx,
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false, &host, &full, 0);
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assert(!(flags & TLB_INVALID_MASK));
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@ -64,7 +64,7 @@ static bool ptw_translate(PTETranslate *inout, hwaddr addr)
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int flags;
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inout->gaddr = addr;
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flags = probe_access_full(inout->env, addr, MMU_DATA_STORE,
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flags = probe_access_full(inout->env, addr, 0, MMU_DATA_STORE,
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inout->ptw_idx, true, &inout->haddr, &full, 0);
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if (unlikely(flags & TLB_INVALID_MASK)) {
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@ -428,7 +428,7 @@ do_check_protect_pse36:
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CPUTLBEntryFull *full;
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int flags, nested_page_size;
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flags = probe_access_full(env, paddr, access_type,
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flags = probe_access_full(env, paddr, 0, access_type,
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MMU_NESTED_IDX, true,
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&pte_trans.haddr, &full, 0);
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if (unlikely(flags & TLB_INVALID_MASK)) {
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