hw/arm/smmuv3: Get prepared for range invalidation
Enhance the smmu_iotlb_inv_iova() helper with range invalidation. This uses the new fields passed in the NH_VA and NH_VAA commands: the size of the range, the level and the granule. As NH_VA and NH_VAA both use those fields, their decoding and handling is factorized in a new smmuv3_s1_range_inval() helper. Signed-off-by: Eric Auger <eric.auger@redhat.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 20200728150815.11446-8-eric.auger@redhat.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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@ -143,15 +143,30 @@ static gboolean smmu_hash_remove_by_asid_iova(gpointer key, gpointer value,
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if (info->asid >= 0 && info->asid != SMMU_IOTLB_ASID(iotlb_key)) {
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return false;
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}
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return (info->iova & ~entry->addr_mask) == entry->iova;
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return ((info->iova & ~entry->addr_mask) == entry->iova) ||
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((entry->iova & ~info->mask) == info->iova);
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}
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inline void smmu_iotlb_inv_iova(SMMUState *s, int asid, dma_addr_t iova)
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inline void
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smmu_iotlb_inv_iova(SMMUState *s, int asid, dma_addr_t iova,
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uint8_t tg, uint64_t num_pages, uint8_t ttl)
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{
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SMMUIOTLBPageInvInfo info = {.asid = asid, .iova = iova};
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if (ttl && (num_pages == 1)) {
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SMMUIOTLBKey key = smmu_get_iotlb_key(asid, iova, tg, ttl);
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trace_smmu_iotlb_inv_iova(asid, iova);
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g_hash_table_foreach_remove(s->iotlb, smmu_hash_remove_by_asid_iova, &info);
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g_hash_table_remove(s->iotlb, &key);
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} else {
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/* if tg is not set we use 4KB range invalidation */
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uint8_t granule = tg ? tg * 2 + 10 : 12;
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SMMUIOTLBPageInvInfo info = {
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.asid = asid, .iova = iova,
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.mask = (num_pages * 1 << granule) - 1};
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g_hash_table_foreach_remove(s->iotlb,
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smmu_hash_remove_by_asid_iova,
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&info);
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}
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}
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inline void smmu_iotlb_inv_asid(SMMUState *s, uint16_t asid)
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@ -298,6 +298,8 @@ enum { /* Command completion notification */
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};
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#define CMD_TYPE(x) extract32((x)->word[0], 0 , 8)
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#define CMD_NUM(x) extract32((x)->word[0], 12 , 5)
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#define CMD_SCALE(x) extract32((x)->word[0], 20 , 5)
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#define CMD_SSEC(x) extract32((x)->word[0], 10, 1)
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#define CMD_SSV(x) extract32((x)->word[0], 11, 1)
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#define CMD_RESUME_AC(x) extract32((x)->word[0], 12, 1)
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@ -310,6 +312,8 @@ enum { /* Command completion notification */
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#define CMD_RESUME_STAG(x) extract32((x)->word[2], 0 , 16)
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#define CMD_RESP(x) extract32((x)->word[2], 11, 2)
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#define CMD_LEAF(x) extract32((x)->word[2], 0 , 1)
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#define CMD_TTL(x) extract32((x)->word[2], 8 , 2)
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#define CMD_TG(x) extract32((x)->word[2], 10, 2)
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#define CMD_STE_RANGE(x) extract32((x)->word[2], 0 , 5)
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#define CMD_ADDR(x) ({ \
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uint64_t high = (uint64_t)(x)->word[3]; \
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@ -785,42 +785,49 @@ epilogue:
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* @n: notifier to be called
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* @asid: address space ID or negative value if we don't care
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* @iova: iova
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* @tg: translation granule (if communicated through range invalidation)
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* @num_pages: number of @granule sized pages (if tg != 0), otherwise 1
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*/
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static void smmuv3_notify_iova(IOMMUMemoryRegion *mr,
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IOMMUNotifier *n,
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int asid,
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dma_addr_t iova)
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int asid, dma_addr_t iova,
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uint8_t tg, uint64_t num_pages)
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{
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SMMUDevice *sdev = container_of(mr, SMMUDevice, iommu);
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SMMUEventInfo event = {.inval_ste_allowed = true};
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SMMUTransTableInfo *tt;
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SMMUTransCfg *cfg;
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IOMMUTLBEntry entry;
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uint8_t granule = tg;
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cfg = smmuv3_get_config(sdev, &event);
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if (!cfg) {
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return;
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}
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if (!tg) {
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SMMUEventInfo event = {.inval_ste_allowed = true};
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SMMUTransCfg *cfg = smmuv3_get_config(sdev, &event);
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SMMUTransTableInfo *tt;
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if (asid >= 0 && cfg->asid != asid) {
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return;
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}
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if (!cfg) {
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return;
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}
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tt = select_tt(cfg, iova);
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if (!tt) {
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return;
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if (asid >= 0 && cfg->asid != asid) {
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return;
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}
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tt = select_tt(cfg, iova);
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if (!tt) {
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return;
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}
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granule = tt->granule_sz;
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}
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entry.target_as = &address_space_memory;
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entry.iova = iova;
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entry.addr_mask = (1 << tt->granule_sz) - 1;
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entry.addr_mask = num_pages * (1 << granule) - 1;
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entry.perm = IOMMU_NONE;
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memory_region_notify_one(n, &entry);
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}
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/* invalidate an asid/iova tuple in all mr's */
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static void smmuv3_inv_notifiers_iova(SMMUState *s, int asid, dma_addr_t iova)
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/* invalidate an asid/iova range tuple in all mr's */
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static void smmuv3_inv_notifiers_iova(SMMUState *s, int asid, dma_addr_t iova,
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uint8_t tg, uint64_t num_pages)
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{
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SMMUDevice *sdev;
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@ -828,28 +835,39 @@ static void smmuv3_inv_notifiers_iova(SMMUState *s, int asid, dma_addr_t iova)
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IOMMUMemoryRegion *mr = &sdev->iommu;
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IOMMUNotifier *n;
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trace_smmuv3_inv_notifiers_iova(mr->parent_obj.name, asid, iova);
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trace_smmuv3_inv_notifiers_iova(mr->parent_obj.name, asid, iova,
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tg, num_pages);
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IOMMU_NOTIFIER_FOREACH(n, mr) {
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smmuv3_notify_iova(mr, n, asid, iova);
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smmuv3_notify_iova(mr, n, asid, iova, tg, num_pages);
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}
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}
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}
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static void smmuv3_s1_range_inval(SMMUState *s, Cmd *cmd)
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{
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uint8_t scale = 0, num = 0, ttl = 0;
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dma_addr_t addr = CMD_ADDR(cmd);
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uint8_t type = CMD_TYPE(cmd);
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uint16_t vmid = CMD_VMID(cmd);
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bool leaf = CMD_LEAF(cmd);
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uint8_t tg = CMD_TG(cmd);
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hwaddr num_pages = 1;
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int asid = -1;
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if (tg) {
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scale = CMD_SCALE(cmd);
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num = CMD_NUM(cmd);
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ttl = CMD_TTL(cmd);
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num_pages = (num + 1) * (1 << (scale));
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}
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if (type == SMMU_CMD_TLBI_NH_VA) {
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asid = CMD_ASID(cmd);
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}
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trace_smmuv3_s1_range_inval(vmid, asid, addr, leaf);
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smmuv3_inv_notifiers_iova(s, asid, addr);
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smmu_iotlb_inv_iova(s, asid, addr);
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trace_smmuv3_s1_range_inval(vmid, asid, addr, tg, num_pages, ttl, leaf);
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smmuv3_inv_notifiers_iova(s, asid, addr, tg, num_pages);
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smmu_iotlb_inv_iova(s, asid, addr, tg, num_pages, ttl);
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}
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static int smmuv3_cmdq_consume(SMMUv3State *s)
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@ -45,11 +45,11 @@ smmuv3_cmdq_cfgi_ste_range(int start, int end) "start=0x%d - end=0x%d"
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smmuv3_cmdq_cfgi_cd(uint32_t sid) "streamid = %d"
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smmuv3_config_cache_hit(uint32_t sid, uint32_t hits, uint32_t misses, uint32_t perc) "Config cache HIT for sid %d (hits=%d, misses=%d, hit rate=%d)"
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smmuv3_config_cache_miss(uint32_t sid, uint32_t hits, uint32_t misses, uint32_t perc) "Config cache MISS for sid %d (hits=%d, misses=%d, hit rate=%d)"
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smmuv3_s1_range_inval(int vmid, int asid, uint64_t addr, bool leaf) "vmid =%d asid =%d addr=0x%"PRIx64" leaf=%d"
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smmuv3_s1_range_inval(int vmid, int asid, uint64_t addr, uint8_t tg, uint64_t num_pages, uint8_t ttl, bool leaf) "vmid =%d asid =%d addr=0x%"PRIx64" tg=%d num_pages=0x%"PRIx64" ttl=%d leaf=%d"
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smmuv3_cmdq_tlbi_nh(void) ""
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smmuv3_cmdq_tlbi_nh_asid(uint16_t asid) "asid=%d"
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smmuv3_config_cache_inv(uint32_t sid) "Config cache INV for sid %d"
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smmuv3_notify_flag_add(const char *iommu) "ADD SMMUNotifier node for iommu mr=%s"
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smmuv3_notify_flag_del(const char *iommu) "DEL SMMUNotifier node for iommu mr=%s"
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smmuv3_inv_notifiers_iova(const char *name, uint16_t asid, uint64_t iova) "iommu mr=%s asid=%d iova=0x%"PRIx64
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smmuv3_inv_notifiers_iova(const char *name, uint16_t asid, uint64_t iova, uint8_t tg, uint64_t num_pages) "iommu mr=%s asid=%d iova=0x%"PRIx64" tg=%d num_pages=0x%"PRIx64
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@ -168,7 +168,8 @@ SMMUIOTLBKey smmu_get_iotlb_key(uint16_t asid, uint64_t iova,
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uint8_t tg, uint8_t level);
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void smmu_iotlb_inv_all(SMMUState *s);
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void smmu_iotlb_inv_asid(SMMUState *s, uint16_t asid);
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void smmu_iotlb_inv_iova(SMMUState *s, int asid, dma_addr_t iova);
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void smmu_iotlb_inv_iova(SMMUState *s, int asid, dma_addr_t iova,
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uint8_t tg, uint64_t num_pages, uint8_t ttl);
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/* Unmap the range of all the notifiers registered to any IOMMU mr */
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void smmu_inv_notifiers_all(SMMUState *s);
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