From d52e94081e626b6b4b181dc7a6fc8f0b98e7d403 Mon Sep 17 00:00:00 2001 From: Kito Cheng Date: Thu, 6 May 2021 00:06:17 +0800 Subject: [PATCH] target/riscv: rvb: support and turn on B-extension from command line B-extension is default off, use cpu rv32 or rv64 with x-b=true to enable B-extension. Signed-off-by: Kito Cheng Signed-off-by: Frank Chang Reviewed-by: Alistair Francis Reviewed-by: Richard Henderson Message-id: 20210505160620.15723-17-frank.chang@sifive.com Signed-off-by: Alistair Francis --- target/riscv/cpu.c | 4 ++++ target/riscv/cpu.h | 1 + 2 files changed, 5 insertions(+) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index ee2523f66b..5702c53c62 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -489,6 +489,9 @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp) if (cpu->cfg.ext_h) { target_misa |= RVH; } + if (cpu->cfg.ext_b) { + target_misa |= RVB; + } if (cpu->cfg.ext_v) { target_misa |= RVV; if (!is_power_of_2(cpu->cfg.vlen)) { @@ -559,6 +562,7 @@ static Property riscv_cpu_properties[] = { DEFINE_PROP_BOOL("s", RISCVCPU, cfg.ext_s, true), DEFINE_PROP_BOOL("u", RISCVCPU, cfg.ext_u, true), /* This is experimental so mark with 'x-' */ + DEFINE_PROP_BOOL("x-b", RISCVCPU, cfg.ext_b, false), DEFINE_PROP_BOOL("x-h", RISCVCPU, cfg.ext_h, false), DEFINE_PROP_BOOL("x-v", RISCVCPU, cfg.ext_v, false), DEFINE_PROP_BOOL("Counters", RISCVCPU, cfg.ext_counters, true), diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index c0c99c3d8d..de9262c930 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -286,6 +286,7 @@ struct RISCVCPU { bool ext_f; bool ext_d; bool ext_c; + bool ext_b; bool ext_s; bool ext_u; bool ext_h;