omap_gpmc: Implement prefetch engine
This commit implements the prefetch engine feature of the GPMC which can be used for NAND devices. This includes both interrupt driven and DMA-filling modes. Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Peter Maydell
parent
eee0a1c67e
commit
d5c8cf993a
257
hw/omap_gpmc.c
257
hw/omap_gpmc.c
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@ -35,6 +35,7 @@ struct omap_gpmc_s {
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uint8_t sysconfig;
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uint16_t irqst;
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uint16_t irqen;
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uint16_t lastirq;
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uint16_t timeout;
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uint16_t config;
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struct omap_gpmc_cs_file_s {
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@ -54,6 +55,8 @@ struct omap_gpmc_s {
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int startengine; /* GPMC_PREFETCH_CONTROL:STARTENGINE */
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int fifopointer; /* GPMC_PREFETCH_STATUS:FIFOPOINTER */
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int count; /* GPMC_PREFETCH_STATUS:COUNTVALUE */
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MemoryRegion iomem;
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uint8_t fifo[64];
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} prefetch;
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};
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@ -76,9 +79,42 @@ static int omap_gpmc_devsize(struct omap_gpmc_cs_file_s *f)
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return (f->config[0] >> 12) & 1;
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}
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/* Extract the chip-select value from the prefetch config1 register */
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static int prefetch_cs(uint32_t config1)
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{
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return (config1 >> 24) & 7;
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}
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static int prefetch_threshold(uint32_t config1)
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{
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return (config1 >> 8) & 0x7f;
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}
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static void omap_gpmc_int_update(struct omap_gpmc_s *s)
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{
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qemu_set_irq(s->irq, s->irqen & s->irqst);
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/* The TRM is a bit unclear, but it seems to say that
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* the TERMINALCOUNTSTATUS bit is set only on the
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* transition when the prefetch engine goes from
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* active to inactive, whereas the FIFOEVENTSTATUS
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* bit is held high as long as the fifo has at
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* least THRESHOLD bytes available.
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* So we do the latter here, but TERMINALCOUNTSTATUS
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* is set elsewhere.
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*/
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if (s->prefetch.fifopointer >= prefetch_threshold(s->prefetch.config1)) {
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s->irqst |= 1;
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}
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if ((s->irqen & s->irqst) != s->lastirq) {
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s->lastirq = s->irqen & s->irqst;
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qemu_set_irq(s->irq, s->lastirq);
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}
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}
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static void omap_gpmc_dma_update(struct omap_gpmc_s *s, int value)
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{
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if (s->prefetch.config1 & 4) {
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qemu_set_irq(s->drq, value);
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}
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}
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/* Access functions for when a NAND-like device is mapped into memory:
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@ -176,6 +212,161 @@ static const MemoryRegionOps omap_nand_ops = {
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.endianness = DEVICE_NATIVE_ENDIAN,
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};
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static void fill_prefetch_fifo(struct omap_gpmc_s *s)
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{
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/* Fill the prefetch FIFO by reading data from NAND.
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* We do this synchronously, unlike the hardware which
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* will do this asynchronously. We refill when the
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* FIFO has THRESHOLD bytes free, and we always refill
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* as much data as possible starting at the top end
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* of the FIFO.
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* (We have to refill at THRESHOLD rather than waiting
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* for the FIFO to empty to allow for the case where
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* the FIFO size isn't an exact multiple of THRESHOLD
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* and we're doing DMA transfers.)
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* This means we never need to handle wrap-around in
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* the fifo-reading code, and the next byte of data
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* to read is always fifo[63 - fifopointer].
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*/
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int fptr;
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int cs = prefetch_cs(s->prefetch.config1);
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int is16bit = (((s->cs_file[cs].config[0] >> 12) & 3) != 0);
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int bytes;
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/* Don't believe the bit of the OMAP TRM that says that COUNTVALUE
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* and TRANSFERCOUNT are in units of 16 bit words for 16 bit NAND.
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* Instead believe the bit that says it is always a byte count.
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*/
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bytes = 64 - s->prefetch.fifopointer;
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if (bytes > s->prefetch.count) {
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bytes = s->prefetch.count;
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}
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s->prefetch.count -= bytes;
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s->prefetch.fifopointer += bytes;
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fptr = 64 - s->prefetch.fifopointer;
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/* Move the existing data in the FIFO so it sits just
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* before what we're about to read in
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*/
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while (fptr < (64 - bytes)) {
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s->prefetch.fifo[fptr] = s->prefetch.fifo[fptr + bytes];
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fptr++;
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}
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while (fptr < 64) {
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if (is16bit) {
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uint32_t v = omap_nand_read(&s->cs_file[cs], 0, 2);
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s->prefetch.fifo[fptr++] = v & 0xff;
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s->prefetch.fifo[fptr++] = (v >> 8) & 0xff;
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} else {
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s->prefetch.fifo[fptr++] = omap_nand_read(&s->cs_file[cs], 0, 1);
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}
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}
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if (s->prefetch.startengine && (s->prefetch.count == 0)) {
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/* This was the final transfer: raise TERMINALCOUNTSTATUS */
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s->irqst |= 2;
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s->prefetch.startengine = 0;
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}
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/* If there are any bytes in the FIFO at this point then
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* we must raise a DMA request (either this is a final part
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* transfer, or we filled the FIFO in which case we certainly
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* have THRESHOLD bytes available)
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*/
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if (s->prefetch.fifopointer != 0) {
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omap_gpmc_dma_update(s, 1);
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}
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omap_gpmc_int_update(s);
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}
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/* Access functions for a NAND-like device when the prefetch/postwrite
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* engine is enabled -- all addresses in the region behave alike:
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* data is read or written to the FIFO.
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*/
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static uint64_t omap_gpmc_prefetch_read(void *opaque, target_phys_addr_t addr,
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unsigned size)
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{
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struct omap_gpmc_s *s = (struct omap_gpmc_s *) opaque;
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uint32_t data;
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if (s->prefetch.config1 & 1) {
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/* The TRM doesn't define the behaviour if you read from the
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* FIFO when the prefetch engine is in write mode. We choose
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* to always return zero.
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*/
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return 0;
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}
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/* Note that trying to read an empty fifo repeats the last byte */
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if (s->prefetch.fifopointer) {
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s->prefetch.fifopointer--;
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}
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data = s->prefetch.fifo[63 - s->prefetch.fifopointer];
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if (s->prefetch.fifopointer ==
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(64 - prefetch_threshold(s->prefetch.config1))) {
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/* We've drained THRESHOLD bytes now. So deassert the
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* DMA request, then refill the FIFO (which will probably
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* assert it again.)
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*/
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omap_gpmc_dma_update(s, 0);
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fill_prefetch_fifo(s);
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}
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omap_gpmc_int_update(s);
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return data;
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}
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static void omap_gpmc_prefetch_write(void *opaque, target_phys_addr_t addr,
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uint64_t value, unsigned size)
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{
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struct omap_gpmc_s *s = (struct omap_gpmc_s *) opaque;
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int cs = prefetch_cs(s->prefetch.config1);
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if ((s->prefetch.config1 & 1) == 0) {
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/* The TRM doesn't define the behaviour of writing to the
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* FIFO when the prefetch engine is in read mode. We
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* choose to ignore the write.
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*/
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return;
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}
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if (s->prefetch.count == 0) {
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/* The TRM doesn't define the behaviour of writing to the
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* FIFO if the transfer is complete. We choose to ignore.
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*/
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return;
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}
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/* The only reason we do any data buffering in postwrite
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* mode is if we are talking to a 16 bit NAND device, in
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* which case we need to buffer the first byte of the
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* 16 bit word until the other byte arrives.
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*/
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int is16bit = (((s->cs_file[cs].config[0] >> 12) & 3) != 0);
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if (is16bit) {
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/* fifopointer alternates between 64 (waiting for first
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* byte of word) and 63 (waiting for second byte)
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*/
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if (s->prefetch.fifopointer == 64) {
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s->prefetch.fifo[0] = value;
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s->prefetch.fifopointer--;
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} else {
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value = (value << 8) | s->prefetch.fifo[0];
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omap_nand_write(&s->cs_file[cs], 0, value, 2);
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s->prefetch.count--;
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s->prefetch.fifopointer = 64;
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}
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} else {
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/* Just write the byte : fifopointer remains 64 at all times */
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omap_nand_write(&s->cs_file[cs], 0, value, 1);
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s->prefetch.count--;
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}
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if (s->prefetch.count == 0) {
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/* Final transfer: raise TERMINALCOUNTSTATUS */
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s->irqst |= 2;
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s->prefetch.startengine = 0;
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}
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omap_gpmc_int_update(s);
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}
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static const MemoryRegionOps omap_prefetch_ops = {
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.read = omap_gpmc_prefetch_read,
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.write = omap_gpmc_prefetch_write,
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.endianness = DEVICE_NATIVE_ENDIAN,
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.impl.min_access_size = 1,
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.impl.max_access_size = 1,
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};
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static MemoryRegion *omap_gpmc_cs_memregion(struct omap_gpmc_s *s, int cs)
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{
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/* Return the MemoryRegion* to map/unmap for this chipselect */
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@ -183,6 +374,11 @@ static MemoryRegion *omap_gpmc_cs_memregion(struct omap_gpmc_s *s, int cs)
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if (omap_gpmc_devtype(f) == OMAP_GPMC_NOR) {
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return f->iomem;
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}
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if ((s->prefetch.config1 & 0x80) &&
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(prefetch_cs(s->prefetch.config1) == cs)) {
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/* The prefetch engine is enabled for this CS: map the FIFO */
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return &s->prefetch.iomem;
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}
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return &f->nandiomem;
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}
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@ -510,24 +706,61 @@ static void omap_gpmc_write(void *opaque, target_phys_addr_t addr,
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break;
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case 0x1e0: /* GPMC_PREFETCH_CONFIG1 */
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s->prefetch.config1 = value & 0x7f8f7fbf;
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/* TODO: update interrupts, fifos, dmas */
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if (!s->prefetch.startengine) {
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uint32_t oldconfig1 = s->prefetch.config1;
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uint32_t changed;
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s->prefetch.config1 = value & 0x7f8f7fbf;
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changed = oldconfig1 ^ s->prefetch.config1;
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if (changed & (0x80 | 0x7000000)) {
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/* Turning the engine on or off, or mapping it somewhere else.
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* cs_map() and cs_unmap() check the prefetch config and
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* overall CSVALID bits, so it is sufficient to unmap-and-map
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* both the old cs and the new one.
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*/
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int oldcs = prefetch_cs(oldconfig1);
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int newcs = prefetch_cs(s->prefetch.config1);
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omap_gpmc_cs_unmap(s, oldcs);
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omap_gpmc_cs_map(s, oldcs);
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if (newcs != oldcs) {
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omap_gpmc_cs_unmap(s, newcs);
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omap_gpmc_cs_map(s, newcs);
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}
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}
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}
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break;
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case 0x1e4: /* GPMC_PREFETCH_CONFIG2 */
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s->prefetch.transfercount = value & 0x3fff;
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if (!s->prefetch.startengine) {
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s->prefetch.transfercount = value & 0x3fff;
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}
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break;
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case 0x1ec: /* GPMC_PREFETCH_CONTROL */
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s->prefetch.startengine = value & 1;
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if (s->prefetch.startengine) {
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if (s->prefetch.config1 & 1) {
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s->prefetch.fifopointer = 0x40;
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if (s->prefetch.startengine != (value & 1)) {
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s->prefetch.startengine = value & 1;
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if (s->prefetch.startengine) {
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/* Prefetch engine start */
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s->prefetch.count = s->prefetch.transfercount;
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if (s->prefetch.config1 & 1) {
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/* Write */
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s->prefetch.fifopointer = 64;
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} else {
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/* Read */
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s->prefetch.fifopointer = 0;
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fill_prefetch_fifo(s);
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}
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} else {
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s->prefetch.fifopointer = 0x00;
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/* Prefetch engine forcibly stopped. The TRM
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* doesn't define the behaviour if you do this.
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* We clear the prefetch count, which means that
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* we permit no more writes, and don't read any
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* more data from NAND. The CPU can still drain
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* the FIFO of unread data.
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*/
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s->prefetch.count = 0;
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}
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omap_gpmc_int_update(s);
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}
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/* TODO: start */
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break;
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case 0x1f4: /* GPMC_ECC_CONFIG */
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@ -579,6 +812,7 @@ struct omap_gpmc_s *omap_gpmc_init(struct omap_mpu_state_s *mpu,
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s->drq = drq;
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s->accept_256 = cpu_is_omap3630(mpu);
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s->revision = cpu_class_omap3(mpu) ? 0x50 : 0x20;
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s->lastirq = 0;
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omap_gpmc_reset(s);
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/* We have to register a different IO memory handler for each
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@ -594,6 +828,9 @@ struct omap_gpmc_s *omap_gpmc_init(struct omap_mpu_state_s *mpu,
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"omap-nand",
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256 * 1024 * 1024);
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}
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memory_region_init_io(&s->prefetch.iomem, &omap_prefetch_ops, s,
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"omap-gpmc-prefetch", 256 * 1024 * 1024);
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return s;
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}
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