PPC: E500: Implement msgsnd
This patch implements the msgsnd instruction. It is part of the Embedded.Processor Control specification and allows one CPU to IPI another CPU without going through an interrupt controller. Signed-off-by: Alexander Graf <agraf@suse.de>
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@ -358,6 +358,7 @@ DEF_HELPER_FLAGS_1(load_sr, TCG_CALL_CONST, tl, tl);
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DEF_HELPER_FLAGS_2(store_sr, TCG_CALL_CONST, void, tl, tl)
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DEF_HELPER_FLAGS_1(602_mfrom, TCG_CALL_CONST | TCG_CALL_PURE, tl, tl)
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DEF_HELPER_1(msgsnd, void, tl)
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DEF_HELPER_1(msgclr, void, tl)
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#endif
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@ -4549,4 +4549,22 @@ void helper_msgclr(target_ulong rb)
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env->pending_interrupts &= ~(1 << irq);
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}
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void helper_msgsnd(target_ulong rb)
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{
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int irq = dbell2irq(rb);
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int pir = rb & DBELL_PIRTAG_MASK;
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CPUState *cenv;
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if (irq < 0) {
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return;
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}
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for (cenv = first_cpu; cenv != NULL; cenv = cenv->next_cpu) {
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if ((rb & DBELL_BRDCAST) || (cenv->spr[SPR_BOOKE_PIR] == pir)) {
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cenv->pending_interrupts |= 1 << irq;
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cpu_interrupt(cenv, CPU_INTERRUPT_HARD);
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}
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}
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}
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#endif /* !CONFIG_USER_ONLY */
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@ -6236,6 +6236,20 @@ static void gen_msgclr(DisasContext *ctx)
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#endif
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}
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static void gen_msgsnd(DisasContext *ctx)
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{
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#if defined(CONFIG_USER_ONLY)
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gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
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#else
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if (unlikely(ctx->mem_idx == 0)) {
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gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
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return;
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}
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gen_helper_msgsnd(cpu_gpr[rB(ctx->opcode)]);
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#endif
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}
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/*** Altivec vector extension ***/
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/* Altivec registers moves */
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@ -8626,6 +8640,8 @@ GEN_HANDLER2_E(tlbivax_booke206, "tlbivax", 0x1F, 0x12, 0x18, 0x00000001,
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PPC_NONE, PPC2_BOOKE206),
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GEN_HANDLER2_E(tlbilx_booke206, "tlbilx", 0x1F, 0x12, 0x00, 0x03800001,
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PPC_NONE, PPC2_BOOKE206),
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GEN_HANDLER2_E(msgsnd, "msgsnd", 0x1F, 0x0E, 0x06, 0x03ff0001,
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PPC_NONE, PPC2_PRCNTL),
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GEN_HANDLER2_E(msgclr, "msgclr", 0x1F, 0x0E, 0x07, 0x03ff0001,
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PPC_NONE, PPC2_PRCNTL),
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GEN_HANDLER(wrtee, 0x1F, 0x03, 0x04, 0x000FFC01, PPC_WRTEE),
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