pci: removed the is_express field since a uniform interface was inserted
according to Eduardo Habkost's commit fd3b02c889
all PCIEs now implement
INTERFACE_PCIE_DEVICE so we don't need is_express field anymore.
Devices that implements only INTERFACE_PCIE_DEVICE (is_express == 1)
or
devices that implements only INTERFACE_CONVENTIONAL_PCI_DEVICE (is_express == 0)
where not affected by the change.
The only devices that were affected are those that are hybrid and also
had (is_express == 1) - therefor only:
- hw/vfio/pci.c
- hw/usb/hcd-xhci.c
- hw/xen/xen_pt.c
For those 3 I made sure that QEMU_PCI_CAP_EXPRESS is on in instance_init()
Reviewed-by: Marcel Apfelbaum <marcel@redhat.com>
Reviewed-by: Eduardo Habkost <ehabkost@redhat.com>
Signed-off-by: Yoni Bettan <ybettan@redhat.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
This commit is contained in:
parent
0ebf9a7488
commit
d61a363d3e
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@ -110,5 +110,5 @@ To enable device hot-plug into the bridge on Linux there're 3 ways:
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Implementation
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==============
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The PCIE-PCI bridge is based on PCI-PCI bridge, but also accumulates PCI Express
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features as a PCI Express device (is_express=1).
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features as a PCI Express device.
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@ -1360,7 +1360,6 @@ static void nvme_class_init(ObjectClass *oc, void *data)
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pc->vendor_id = PCI_VENDOR_ID_INTEL;
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pc->device_id = 0x5845;
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pc->revision = 2;
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pc->is_express = 1;
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set_bit(DEVICE_CATEGORY_STORAGE, dc->categories);
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dc->desc = "Non-Volatile Memory Express";
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@ -675,7 +675,6 @@ static void e1000e_class_init(ObjectClass *class, void *data)
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c->revision = 0;
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c->romfile = "efi-e1000e.rom";
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c->class_id = PCI_CLASS_NETWORK_ETHERNET;
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c->is_express = 1;
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dc->desc = "Intel 82574L GbE Controller";
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dc->reset = e1000e_qdev_reset;
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@ -170,7 +170,6 @@ static void pcie_pci_bridge_class_init(ObjectClass *klass, void *data)
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DeviceClass *dc = DEVICE_CLASS(klass);
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HotplugHandlerClass *hc = HOTPLUG_HANDLER_CLASS(klass);
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k->is_express = 1;
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k->is_bridge = 1;
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k->vendor_id = PCI_VENDOR_ID_REDHAT;
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k->device_id = PCI_DEVICE_ID_REDHAT_PCIE_BRIDGE;
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@ -145,7 +145,6 @@ static void rp_class_init(ObjectClass *klass, void *data)
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DeviceClass *dc = DEVICE_CLASS(klass);
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PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
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k->is_express = 1;
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k->is_bridge = 1;
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k->config_write = rp_write_config;
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k->realize = rp_realize;
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@ -178,7 +178,6 @@ static void xio3130_downstream_class_init(ObjectClass *klass, void *data)
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DeviceClass *dc = DEVICE_CLASS(klass);
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PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
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k->is_express = 1;
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k->is_bridge = 1;
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k->config_write = xio3130_downstream_write_config;
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k->realize = xio3130_downstream_realize;
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@ -149,7 +149,6 @@ static void xio3130_upstream_class_init(ObjectClass *klass, void *data)
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DeviceClass *dc = DEVICE_CLASS(klass);
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PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
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k->is_express = 1;
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k->is_bridge = 1;
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k->config_write = xio3130_upstream_write_config;
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k->realize = xio3130_upstream_realize;
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@ -297,7 +297,6 @@ static void xilinx_pcie_root_class_init(ObjectClass *klass, void *data)
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k->device_id = 0x7021;
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k->revision = 0;
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k->class_id = PCI_CLASS_BRIDGE_HOST;
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k->is_express = true;
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k->is_bridge = true;
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k->realize = xilinx_pcie_root_realize;
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k->exit = pci_bridge_exitfn;
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@ -2005,11 +2005,15 @@ static void pci_qdev_realize(DeviceState *qdev, Error **errp)
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{
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PCIDevice *pci_dev = (PCIDevice *)qdev;
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PCIDeviceClass *pc = PCI_DEVICE_GET_CLASS(pci_dev);
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ObjectClass *klass = OBJECT_CLASS(pc);
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Error *local_err = NULL;
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bool is_default_rom;
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/* initialize cap_present for pci_is_express() and pci_config_size() */
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if (pc->is_express) {
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/* initialize cap_present for pci_is_express() and pci_config_size(),
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* Note that hybrid PCIs are not set automatically and need to manage
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* QEMU_PCI_CAP_EXPRESS manually */
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if (object_class_dynamic_cast(klass, INTERFACE_PCIE_DEVICE) &&
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!object_class_dynamic_cast(klass, INTERFACE_CONVENTIONAL_PCI_DEVICE)) {
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pci_dev->cap_present |= QEMU_PCI_CAP_EXPRESS;
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}
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@ -2447,7 +2447,6 @@ typedef struct MegasasInfo {
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uint16_t subsystem_id;
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int ioport_bar;
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int mmio_bar;
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bool is_express;
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int osts;
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const VMStateDescription *vmsd;
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Property *props;
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@ -2465,7 +2464,6 @@ static struct MegasasInfo megasas_devices[] = {
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.ioport_bar = 2,
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.mmio_bar = 0,
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.osts = MFI_1078_RM | 1,
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.is_express = false,
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.vmsd = &vmstate_megasas_gen1,
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.props = megasas_properties_gen1,
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.interfaces = (InterfaceInfo[]) {
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@ -2482,7 +2480,6 @@ static struct MegasasInfo megasas_devices[] = {
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.ioport_bar = 0,
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.mmio_bar = 1,
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.osts = MFI_GEN2_RM,
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.is_express = true,
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.vmsd = &vmstate_megasas_gen2,
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.props = megasas_properties_gen2,
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.interfaces = (InterfaceInfo[]) {
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@ -2506,7 +2503,6 @@ static void megasas_class_init(ObjectClass *oc, void *data)
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pc->subsystem_vendor_id = PCI_VENDOR_ID_LSI_LOGIC;
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pc->subsystem_id = info->subsystem_id;
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pc->class_id = PCI_CLASS_STORAGE_RAID;
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pc->is_express = info->is_express;
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e->mmio_bar = info->mmio_bar;
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e->ioport_bar = info->ioport_bar;
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e->osts = info->osts;
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@ -3649,6 +3649,13 @@ static Property xhci_properties[] = {
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DEFINE_PROP_END_OF_LIST(),
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};
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static void xhci_instance_init(Object *obj)
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{
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/* QEMU_PCI_CAP_EXPRESS initialization does not depend on QEMU command
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* line, therefore, no need to wait to realize like other devices */
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PCI_DEVICE(obj)->cap_present |= QEMU_PCI_CAP_EXPRESS;
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}
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static void xhci_class_init(ObjectClass *klass, void *data)
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{
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PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
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@ -3661,7 +3668,6 @@ static void xhci_class_init(ObjectClass *klass, void *data)
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k->realize = usb_xhci_realize;
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k->exit = usb_xhci_exit;
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k->class_id = PCI_CLASS_SERIAL_USB;
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k->is_express = 1;
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}
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static const TypeInfo xhci_info = {
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@ -3669,6 +3675,7 @@ static const TypeInfo xhci_info = {
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.parent = TYPE_PCI_DEVICE,
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.instance_size = sizeof(XHCIState),
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.class_init = xhci_class_init,
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.instance_init = xhci_instance_init,
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.abstract = true,
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.interfaces = (InterfaceInfo[]) {
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{ INTERFACE_PCIE_DEVICE },
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@ -3113,6 +3113,10 @@ static void vfio_instance_init(Object *obj)
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vdev->host.function = ~0U;
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vdev->nv_gpudirect_clique = 0xFF;
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/* QEMU_PCI_CAP_EXPRESS initialization does not depend on QEMU command
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* line, therefore, no need to wait to realize like other devices */
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pci_dev->cap_present |= QEMU_PCI_CAP_EXPRESS;
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}
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static Property vfio_pci_dev_properties[] = {
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@ -3171,7 +3175,6 @@ static void vfio_pci_dev_class_init(ObjectClass *klass, void *data)
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pdc->exit = vfio_exitfn;
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pdc->config_read = vfio_pci_read_config;
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pdc->config_write = vfio_pci_write_config;
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pdc->is_express = 1; /* We might be */
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}
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static const TypeInfo vfio_pci_dev_info = {
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@ -937,6 +937,13 @@ static Property xen_pci_passthrough_properties[] = {
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DEFINE_PROP_END_OF_LIST(),
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};
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static void xen_pci_passthrough_instance_init(Object *obj)
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{
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/* QEMU_PCI_CAP_EXPRESS initialization does not depend on QEMU command
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* line, therefore, no need to wait to realize like other devices */
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PCI_DEVICE(obj)->cap_present |= QEMU_PCI_CAP_EXPRESS;
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}
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static void xen_pci_passthrough_class_init(ObjectClass *klass, void *data)
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{
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DeviceClass *dc = DEVICE_CLASS(klass);
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k->exit = xen_pt_unregister_device;
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k->config_read = xen_pt_pci_read_config;
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k->config_write = xen_pt_pci_write_config;
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k->is_express = 1; /* We might be */
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set_bit(DEVICE_CATEGORY_MISC, dc->categories);
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dc->desc = "Assign an host PCI device with Xen";
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dc->props = xen_pci_passthrough_properties;
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.instance_size = sizeof(XenPCIPassthroughState),
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.instance_finalize = xen_pci_passthrough_finalize,
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.class_init = xen_pci_passthrough_class_init,
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.instance_init = xen_pci_passthrough_instance_init,
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.interfaces = (InterfaceInfo[]) {
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{ INTERFACE_CONVENTIONAL_PCI_DEVICE },
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{ INTERFACE_PCIE_DEVICE },
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@ -236,9 +236,6 @@ typedef struct PCIDeviceClass {
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*/
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int is_bridge;
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/* pcie stuff */
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int is_express; /* is this device pci express? */
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/* rom bar */
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const char *romfile;
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} PCIDeviceClass;
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