diff --git a/target/hexagon/genptr.c b/target/hexagon/genptr.c
index 66a968c884..90db99024f 100644
--- a/target/hexagon/genptr.c
+++ b/target/hexagon/genptr.c
@@ -43,6 +43,33 @@ TCGv gen_read_preg(TCGv pred, uint8_t num)
return pred;
}
+#define IMMUTABLE (~0)
+
+static const target_ulong reg_immut_masks[TOTAL_PER_THREAD_REGS] = {
+ [HEX_REG_USR] = 0xc13000c0,
+ [HEX_REG_PC] = IMMUTABLE,
+ [HEX_REG_GP] = 0x3f,
+ [HEX_REG_UPCYCLELO] = IMMUTABLE,
+ [HEX_REG_UPCYCLEHI] = IMMUTABLE,
+ [HEX_REG_UTIMERLO] = IMMUTABLE,
+ [HEX_REG_UTIMERHI] = IMMUTABLE,
+};
+
+static inline void gen_masked_reg_write(TCGv new_val, TCGv cur_val,
+ target_ulong reg_mask)
+{
+ if (reg_mask) {
+ TCGv tmp = tcg_temp_new();
+
+ /* new_val = (new_val & ~reg_mask) | (cur_val & reg_mask) */
+ tcg_gen_andi_tl(new_val, new_val, ~reg_mask);
+ tcg_gen_andi_tl(tmp, cur_val, reg_mask);
+ tcg_gen_or_tl(new_val, new_val, tmp);
+
+ tcg_temp_free(tmp);
+ }
+}
+
static inline void gen_log_predicated_reg_write(int rnum, TCGv val,
uint32_t slot)
{
@@ -69,6 +96,9 @@ static inline void gen_log_predicated_reg_write(int rnum, TCGv val,
void gen_log_reg_write(int rnum, TCGv val)
{
+ const target_ulong reg_mask = reg_immut_masks[rnum];
+
+ gen_masked_reg_write(val, hex_gpr[rnum], reg_mask);
tcg_gen_mov_tl(hex_new_value[rnum], val);
if (HEX_DEBUG) {
/* Do this so HELPER(debug_commit_end) will know */
@@ -114,19 +144,29 @@ static void gen_log_predicated_reg_write_pair(int rnum, TCGv_i64 val,
static void gen_log_reg_write_pair(int rnum, TCGv_i64 val)
{
+ const target_ulong reg_mask_low = reg_immut_masks[rnum];
+ const target_ulong reg_mask_high = reg_immut_masks[rnum + 1];
+ TCGv val32 = tcg_temp_new();
+
/* Low word */
- tcg_gen_extrl_i64_i32(hex_new_value[rnum], val);
+ tcg_gen_extrl_i64_i32(val32, val);
+ gen_masked_reg_write(val32, hex_gpr[rnum], reg_mask_low);
+ tcg_gen_mov_tl(hex_new_value[rnum], val32);
if (HEX_DEBUG) {
/* Do this so HELPER(debug_commit_end) will know */
tcg_gen_movi_tl(hex_reg_written[rnum], 1);
}
/* High word */
- tcg_gen_extrh_i64_i32(hex_new_value[rnum + 1], val);
+ tcg_gen_extrh_i64_i32(val32, val);
+ gen_masked_reg_write(val32, hex_gpr[rnum + 1], reg_mask_high);
+ tcg_gen_mov_tl(hex_new_value[rnum + 1], val32);
if (HEX_DEBUG) {
/* Do this so HELPER(debug_commit_end) will know */
tcg_gen_movi_tl(hex_reg_written[rnum + 1], 1);
}
+
+ tcg_temp_free(val32);
}
void gen_log_pred_write(DisasContext *ctx, int pnum, TCGv val)
diff --git a/tests/tcg/hexagon/Makefile.target b/tests/tcg/hexagon/Makefile.target
index f1378d86a9..18e6a5969e 100644
--- a/tests/tcg/hexagon/Makefile.target
+++ b/tests/tcg/hexagon/Makefile.target
@@ -44,6 +44,7 @@ HEX_TESTS += atomics
HEX_TESTS += fpstuff
HEX_TESTS += overflow
HEX_TESTS += signal_context
+HEX_TESTS += reg_mut
HEX_TESTS += test_abs
HEX_TESTS += test_bitcnt
diff --git a/tests/tcg/hexagon/reg_mut.c b/tests/tcg/hexagon/reg_mut.c
new file mode 100644
index 0000000000..910e663ace
--- /dev/null
+++ b/tests/tcg/hexagon/reg_mut.c
@@ -0,0 +1,152 @@
+
+/*
+ * Copyright(c) 2022 Qualcomm Innovation Center, Inc. All Rights Reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, see .
+ */
+
+#include
+#include
+
+static int err;
+
+#define check(N, EXPECT) \
+ do { \
+ uint64_t value = N; \
+ uint64_t expect = EXPECT; \
+ if (value != EXPECT) { \
+ printf("ERROR: \"%s\" 0x%04llx != 0x%04llx at %s:%d\n", #N, value, \
+ expect, __FILE__, __LINE__); \
+ err++; \
+ } \
+ } while (0)
+
+#define check_ne(N, EXPECT) \
+ do { \
+ uint64_t value = N; \
+ uint64_t expect = EXPECT; \
+ if (value == EXPECT) { \
+ printf("ERROR: \"%s\" 0x%04llx == 0x%04llx at %s:%d\n", #N, value, \
+ expect, __FILE__, __LINE__); \
+ err++; \
+ } \
+ } while (0)
+
+#define WRITE_REG_NOCLOBBER(output, reg_name, input) \
+ asm volatile(reg_name " = %1\n\t" \
+ "%0 = " reg_name "\n\t" \
+ : "=r"(output) \
+ : "r"(input) \
+ : );
+
+#define WRITE_REG_ENCODED(output, reg_name, input, encoding) \
+ asm volatile("r0 = %1\n\t" \
+ encoding "\n\t" \
+ "%0 = " reg_name "\n\t" \
+ : "=r"(output) \
+ : "r"(input) \
+ : "r0");
+
+#define WRITE_REG_PAIR_ENCODED(output, reg_name, input, encoding) \
+ asm volatile("r1:0 = %1\n\t" \
+ encoding "\n\t" \
+ "%0 = " reg_name "\n\t" \
+ : "=r"(output) \
+ : "r"(input) \
+ : "r1:0");
+
+/*
+ * Instruction word: { pc = r0 }
+ *
+ * This instruction is barred by the assembler.
+ *
+ * 3 2 1
+ * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
+ * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
+ * | Opc[A2_tfrrcr] | Src[R0] |P P| | C9/PC |
+ * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
+ */
+#define PC_EQ_R0 ".word 0x6220c009"
+#define C9_8_EQ_R1_0 ".word 0x6320c008"
+
+static inline void write_control_registers(void)
+{
+ uint32_t result = 0;
+
+ WRITE_REG_NOCLOBBER(result, "usr", 0xffffffff);
+ check(result, 0x3ecfff3f);
+
+ WRITE_REG_NOCLOBBER(result, "gp", 0xffffffff);
+ check(result, 0xffffffc0);
+
+ WRITE_REG_NOCLOBBER(result, "upcyclelo", 0xffffffff);
+ check(result, 0x00000000);
+
+ WRITE_REG_NOCLOBBER(result, "upcyclehi", 0xffffffff);
+ check(result, 0x00000000);
+
+ WRITE_REG_NOCLOBBER(result, "utimerlo", 0xffffffff);
+ check(result, 0x00000000);
+
+ WRITE_REG_NOCLOBBER(result, "utimerhi", 0xffffffff);
+ check(result, 0x00000000);
+
+ /*
+ * PC is special. Setting it to these values
+ * should cause a catastrophic failure.
+ */
+ WRITE_REG_ENCODED(result, "pc", 0x00000000, PC_EQ_R0);
+ check_ne(result, 0x00000000);
+
+ WRITE_REG_ENCODED(result, "pc", 0x00000001, PC_EQ_R0);
+ check_ne(result, 0x00000001);
+
+ WRITE_REG_ENCODED(result, "pc", 0xffffffff, PC_EQ_R0);
+ check_ne(result, 0xffffffff);
+}
+
+static inline void write_control_register_pairs(void)
+{
+ uint64_t result = 0;
+
+ WRITE_REG_NOCLOBBER(result, "c11:10", 0xffffffffffffffff);
+ check(result, 0xffffffc0ffffffff);
+
+ WRITE_REG_NOCLOBBER(result, "c15:14", 0xffffffffffffffff);
+ check(result, 0x0000000000000000);
+
+ WRITE_REG_NOCLOBBER(result, "c31:30", 0xffffffffffffffff);
+ check(result, 0x0000000000000000);
+
+ WRITE_REG_PAIR_ENCODED(result, "c9:8", (uint64_t) 0x0000000000000000,
+ C9_8_EQ_R1_0);
+ check_ne(result, 0x000000000000000);
+
+ WRITE_REG_PAIR_ENCODED(result, "c9:8", 0x0000000100000000, C9_8_EQ_R1_0);
+ check_ne(result, 0x0000000100000000);
+
+ WRITE_REG_PAIR_ENCODED(result, "c9:8", 0xffffffffffffffff, C9_8_EQ_R1_0);
+ check_ne(result, 0xffffffffffffffff);
+}
+
+int main()
+{
+ err = 0;
+
+ write_control_registers();
+ write_control_register_pairs();
+
+ puts(err ? "FAIL" : "PASS");
+ return err;
+}