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hw/sparc/leon3: implement multiprocessor

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This allows to register more than one CPU on the leon3_generic machine.

Co-developed-by: Frederic Konrad <konrad.frederic@yahoo.fr>
Signed-off-by: Clément Chigot <chigot@adacore.com>
Message-ID: <20240131085047.18458-8-chigot@adacore.com>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
This commit is contained in:
Clément Chigot 2024-01-31 09:50:45 +01:00 committed by Philippe Mathieu-Daudé
parent 92688a91c3
commit d65aba8286
1 changed files with 68 additions and 25 deletions
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93
hw/sparc/leon3.c
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@ -54,6 +54,8 @@
#define LEON3_PROM_OFFSET (0x00000000) #define LEON3_PROM_OFFSET (0x00000000)
#define LEON3_RAM_OFFSET (0x40000000) #define LEON3_RAM_OFFSET (0x40000000)
#define MAX_CPUS 4
#define LEON3_UART_OFFSET (0x80000100) #define LEON3_UART_OFFSET (0x80000100)
#define LEON3_UART_IRQ (3) #define LEON3_UART_IRQ (3)
@ -67,8 +69,11 @@
#define LEON3_AHB_PNP_OFFSET (0xFFFFF000) #define LEON3_AHB_PNP_OFFSET (0xFFFFF000)
typedef struct ResetData { typedef struct ResetData {
SPARCCPU *cpu; struct CPUResetData {
uint32_t entry; /* save kernel entry in case of reset */ int id;
SPARCCPU *cpu;
} info[MAX_CPUS];
uint32_t entry; /* save kernel entry in case of reset */
} ResetData; } ResetData;
static uint32_t *gen_store_u32(uint32_t *code, hwaddr addr, uint32_t val) static uint32_t *gen_store_u32(uint32_t *code, hwaddr addr, uint32_t val)
@ -123,17 +128,19 @@ static void write_bootloader(void *ptr, hwaddr kernel_addr)
stl_p(p++, 0x01000000); /* nop */ stl_p(p++, 0x01000000); /* nop */
} }
static void main_cpu_reset(void *opaque) static void leon3_cpu_reset(void *opaque)
{ {
ResetData *s = (ResetData *)opaque; struct CPUResetData *info = (struct CPUResetData *) opaque;
CPUState *cpu = CPU(s->cpu); int id = info->id;
CPUSPARCState *env = &s->cpu->env; ResetData *s = (ResetData *)DO_UPCAST(ResetData, info[id], info);
CPUState *cpu = CPU(s->info[id].cpu);
CPUSPARCState *env = cpu_env(cpu);
cpu_reset(cpu); cpu_reset(cpu);
cpu->halted = 0; cpu->halted = cpu->cpu_index != 0;
env->pc = s->entry; env->pc = s->entry;
env->npc = s->entry + 4; env->npc = s->entry + 4;
} }
static void leon3_cache_control_int(CPUSPARCState *env) static void leon3_cache_control_int(CPUSPARCState *env)
@ -167,8 +174,8 @@ static void leon3_cache_control_int(CPUSPARCState *env)
static void leon3_irq_ack(CPUSPARCState *env, int intno) static void leon3_irq_ack(CPUSPARCState *env, int intno)
{ {
/* No SMP support yet, only CPU #0 available so far. */ CPUState *cpu = CPU(env_cpu(env));
grlib_irqmp_ack(env->irq_manager, 0, intno); grlib_irqmp_ack(env->irq_manager, cpu->cpu_index, intno);
} }
/* /*
@ -210,6 +217,19 @@ static void leon3_set_pil_in(void *opaque, int n, int level)
} }
} }
static void leon3_start_cpu_async_work(CPUState *cpu, run_on_cpu_data data)
{
cpu->halted = 0;
}
static void leon3_start_cpu(void *opaque, int n, int level)
{
CPUState *cs = CPU(opaque);
assert(level == 1);
async_run_on_cpu(cs, leon3_start_cpu_async_work, RUN_ON_CPU_NULL);
}
static void leon3_irq_manager(CPUSPARCState *env, int intno) static void leon3_irq_manager(CPUSPARCState *env, int intno)
{ {
leon3_irq_ack(env, intno); leon3_irq_ack(env, intno);
@ -235,16 +255,20 @@ static void leon3_generic_hw_init(MachineState *machine)
AHBPnp *ahb_pnp; AHBPnp *ahb_pnp;
APBPnp *apb_pnp; APBPnp *apb_pnp;
/* Init CPU */ reset_info = g_malloc0(sizeof(ResetData));
cpu = SPARC_CPU(cpu_create(machine->cpu_type));
env = &cpu->env;
cpu_sparc_set_id(env, 0); for (i = 0; i < machine->smp.cpus; i++) {
/* Init CPU */
cpu = SPARC_CPU(cpu_create(machine->cpu_type));
env = &cpu->env;
/* Reset data */ cpu_sparc_set_id(env, i);
reset_info = g_new0(ResetData, 1);
reset_info->cpu = cpu; /* Reset data */
qemu_register_reset(main_cpu_reset, reset_info); reset_info->info[i].id = i;
reset_info->info[i].cpu = cpu;
qemu_register_reset(leon3_cpu_reset, &reset_info->info[i]);
}
ahb_pnp = GRLIB_AHB_PNP(qdev_new(TYPE_GRLIB_AHB_PNP)); ahb_pnp = GRLIB_AHB_PNP(qdev_new(TYPE_GRLIB_AHB_PNP));
sysbus_realize_and_unref(SYS_BUS_DEVICE(ahb_pnp), &error_fatal); sysbus_realize_and_unref(SYS_BUS_DEVICE(ahb_pnp), &error_fatal);
@ -262,14 +286,28 @@ static void leon3_generic_hw_init(MachineState *machine)
/* Allocate IRQ manager */ /* Allocate IRQ manager */
irqmpdev = qdev_new(TYPE_GRLIB_IRQMP); irqmpdev = qdev_new(TYPE_GRLIB_IRQMP);
object_property_set_int(OBJECT(irqmpdev), "ncpus", machine->smp.cpus,
&error_fatal);
sysbus_realize_and_unref(SYS_BUS_DEVICE(irqmpdev), &error_fatal); sysbus_realize_and_unref(SYS_BUS_DEVICE(irqmpdev), &error_fatal);
qdev_init_gpio_in_named_with_opaque(DEVICE(cpu), leon3_set_pil_in,
env, "pil", 1); for (i = 0; i < machine->smp.cpus; i++) {
qdev_connect_gpio_out_named(irqmpdev, "grlib-irq", 0, cpu = reset_info->info[i].cpu;
qdev_get_gpio_in_named(DEVICE(cpu), "pil", 0)); env = &cpu->env;
qdev_init_gpio_in_named_with_opaque(DEVICE(cpu), leon3_start_cpu,
cpu, "start_cpu", 1);
qdev_connect_gpio_out_named(irqmpdev, "grlib-start-cpu", i,
qdev_get_gpio_in_named(DEVICE(cpu),
"start_cpu", 0));
qdev_init_gpio_in_named_with_opaque(DEVICE(cpu), leon3_set_pil_in,
env, "pil", 1);
qdev_connect_gpio_out_named(irqmpdev, "grlib-irq", i,
qdev_get_gpio_in_named(DEVICE(cpu),
"pil", 0));
env->irq_manager = irqmpdev;
env->qemu_irq_ack = leon3_irq_manager;
}
sysbus_mmio_map(SYS_BUS_DEVICE(irqmpdev), 0, LEON3_IRQMP_OFFSET); sysbus_mmio_map(SYS_BUS_DEVICE(irqmpdev), 0, LEON3_IRQMP_OFFSET);
env->irq_manager = irqmpdev;
env->qemu_irq_ack = leon3_irq_manager;
grlib_apb_pnp_add_entry(apb_pnp, LEON3_IRQMP_OFFSET, 0xFFF, grlib_apb_pnp_add_entry(apb_pnp, LEON3_IRQMP_OFFSET, 0xFFF,
GRLIB_VENDOR_GAISLER, GRLIB_IRQMP_DEV, GRLIB_VENDOR_GAISLER, GRLIB_IRQMP_DEV,
2, 0, GRLIB_APBIO_AREA); 2, 0, GRLIB_APBIO_AREA);
@ -342,6 +380,10 @@ static void leon3_generic_hw_init(MachineState *machine)
*/ */
write_bootloader(memory_region_get_ram_ptr(prom), entry); write_bootloader(memory_region_get_ram_ptr(prom), entry);
reset_info->entry = LEON3_PROM_OFFSET; reset_info->entry = LEON3_PROM_OFFSET;
for (i = 0; i < machine->smp.cpus; i++) {
reset_info->info[i].cpu->env.pc = LEON3_PROM_OFFSET;
reset_info->info[i].cpu->env.npc = LEON3_PROM_OFFSET + 4;
}
} }
} }
@ -380,6 +422,7 @@ static void leon3_generic_machine_init(MachineClass *mc)
mc->init = leon3_generic_hw_init; mc->init = leon3_generic_hw_init;
mc->default_cpu_type = SPARC_CPU_TYPE_NAME("LEON3"); mc->default_cpu_type = SPARC_CPU_TYPE_NAME("LEON3");
mc->default_ram_id = "leon3.ram"; mc->default_ram_id = "leon3.ram";
mc->max_cpus = MAX_CPUS;
} }
DEFINE_MACHINE("leon3_generic", leon3_generic_machine_init) DEFINE_MACHINE("leon3_generic", leon3_generic_machine_init)