target/sh4: Recognize common gUSA sequences
For many of the sequences produced by gcc or glibc, we can translate these as host atomic operations. Which saves the need to acquire the exclusive lock. Signed-off-by: Richard Henderson <rth@twiddle.net> Message-Id: <20170718200255.31647-8-rth@twiddle.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
This commit is contained in:
Richard Henderson
Aurelien Jarno
parent
4bfa602bc2
commit
d6a6cffdd3
@ -1869,10 +1869,17 @@ static void decode_opc(DisasContext * ctx)
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*/
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static int decode_gusa(DisasContext *ctx, CPUSH4State *env, int *pmax_insns)
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{
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uint16_t insns[5];
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int ld_adr, ld_dst, ld_mop;
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int op_dst, op_src, op_opc;
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int mv_src, mt_dst, st_src, st_mop;
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TCGv op_arg;
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uint32_t pc = ctx->pc;
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uint32_t pc_end = ctx->tb->cs_base;
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int backup = sextract32(ctx->tbflags, GUSA_SHIFT, 8);
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int max_insns = (pc_end - pc) / 2;
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int i;
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if (pc != pc_end + backup || max_insns < 2) {
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/* This is a malformed gUSA region. Don't do anything special,
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@ -1889,6 +1896,320 @@ static int decode_gusa(DisasContext *ctx, CPUSH4State *env, int *pmax_insns)
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return 0;
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}
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/* The state machine below will consume only a few insns.
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If there are more than that in a region, fail now. */
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if (max_insns > ARRAY_SIZE(insns)) {
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goto fail;
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}
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/* Read all of the insns for the region. */
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for (i = 0; i < max_insns; ++i) {
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insns[i] = cpu_lduw_code(env, pc + i * 2);
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}
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ld_adr = ld_dst = ld_mop = -1;
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mv_src = -1;
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op_dst = op_src = op_opc = -1;
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mt_dst = -1;
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st_src = st_mop = -1;
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TCGV_UNUSED(op_arg);
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i = 0;
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#define NEXT_INSN \
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do { if (i >= max_insns) goto fail; ctx->opcode = insns[i++]; } while (0)
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/*
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* Expect a load to begin the region.
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*/
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NEXT_INSN;
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switch (ctx->opcode & 0xf00f) {
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case 0x6000: /* mov.b @Rm,Rn */
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ld_mop = MO_SB;
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break;
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case 0x6001: /* mov.w @Rm,Rn */
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ld_mop = MO_TESW;
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break;
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case 0x6002: /* mov.l @Rm,Rn */
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ld_mop = MO_TESL;
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break;
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default:
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goto fail;
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}
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ld_adr = B7_4;
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ld_dst = B11_8;
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if (ld_adr == ld_dst) {
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goto fail;
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}
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/* Unless we see a mov, any two-operand operation must use ld_dst. */
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op_dst = ld_dst;
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/*
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* Expect an optional register move.
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*/
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NEXT_INSN;
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switch (ctx->opcode & 0xf00f) {
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case 0x6003: /* mov Rm,Rn */
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/* Here we want to recognize ld_dst being saved for later consumtion,
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or for another input register being copied so that ld_dst need not
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be clobbered during the operation. */
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op_dst = B11_8;
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mv_src = B7_4;
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if (op_dst == ld_dst) {
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/* Overwriting the load output. */
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goto fail;
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}
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if (mv_src != ld_dst) {
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/* Copying a new input; constrain op_src to match the load. */
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op_src = ld_dst;
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}
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break;
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default:
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/* Put back and re-examine as operation. */
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--i;
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}
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/*
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* Expect the operation.
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*/
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NEXT_INSN;
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switch (ctx->opcode & 0xf00f) {
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case 0x300c: /* add Rm,Rn */
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op_opc = INDEX_op_add_i32;
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goto do_reg_op;
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case 0x2009: /* and Rm,Rn */
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op_opc = INDEX_op_and_i32;
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goto do_reg_op;
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case 0x200a: /* xor Rm,Rn */
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op_opc = INDEX_op_xor_i32;
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goto do_reg_op;
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case 0x200b: /* or Rm,Rn */
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op_opc = INDEX_op_or_i32;
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do_reg_op:
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/* The operation register should be as expected, and the
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other input cannot depend on the load. */
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if (op_dst != B11_8) {
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goto fail;
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}
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if (op_src < 0) {
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/* Unconstrainted input. */
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op_src = B7_4;
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} else if (op_src == B7_4) {
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/* Constrained input matched load. All operations are
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commutative; "swap" them by "moving" the load output
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to the (implicit) first argument and the move source
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to the (explicit) second argument. */
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op_src = mv_src;
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} else {
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goto fail;
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}
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op_arg = REG(op_src);
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break;
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case 0x6007: /* not Rm,Rn */
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if (ld_dst != B7_4 || mv_src >= 0) {
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goto fail;
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}
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op_dst = B11_8;
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op_opc = INDEX_op_xor_i32;
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op_arg = tcg_const_i32(-1);
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break;
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case 0x7000 ... 0x700f: /* add #imm,Rn */
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if (op_dst != B11_8 || mv_src >= 0) {
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goto fail;
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}
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op_opc = INDEX_op_add_i32;
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op_arg = tcg_const_i32(B7_0s);
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break;
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case 0x3000: /* cmp/eq Rm,Rn */
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/* Looking for the middle of a compare-and-swap sequence,
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beginning with the compare. Operands can be either order,
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but with only one overlapping the load. */
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if ((ld_dst == B11_8) + (ld_dst == B7_4) != 1 || mv_src >= 0) {
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goto fail;
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}
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op_opc = INDEX_op_setcond_i32; /* placeholder */
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op_src = (ld_dst == B11_8 ? B7_4 : B11_8);
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op_arg = REG(op_src);
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NEXT_INSN;
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switch (ctx->opcode & 0xff00) {
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case 0x8b00: /* bf label */
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case 0x8f00: /* bf/s label */
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if (pc + (i + 1 + B7_0s) * 2 != pc_end) {
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goto fail;
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}
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if ((ctx->opcode & 0xff00) == 0x8b00) { /* bf label */
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break;
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}
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/* We're looking to unconditionally modify Rn with the
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result of the comparison, within the delay slot of
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the branch. This is used by older gcc. */
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NEXT_INSN;
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if ((ctx->opcode & 0xf0ff) == 0x0029) { /* movt Rn */
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mt_dst = B11_8;
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} else {
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goto fail;
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}
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break;
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default:
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goto fail;
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}
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break;
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case 0x2008: /* tst Rm,Rn */
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/* Looking for a compare-and-swap against zero. */
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if (ld_dst != B11_8 || ld_dst != B7_4 || mv_src >= 0) {
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goto fail;
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}
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op_opc = INDEX_op_setcond_i32;
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op_arg = tcg_const_i32(0);
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NEXT_INSN;
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if ((ctx->opcode & 0xff00) != 0x8900 /* bt label */
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|| pc + (i + 1 + B7_0s) * 2 != pc_end) {
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goto fail;
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}
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break;
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default:
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/* Put back and re-examine as store. */
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--i;
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}
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/*
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* Expect the store.
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*/
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/* The store must be the last insn. */
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if (i != max_insns - 1) {
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goto fail;
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}
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NEXT_INSN;
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switch (ctx->opcode & 0xf00f) {
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case 0x2000: /* mov.b Rm,@Rn */
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st_mop = MO_UB;
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break;
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case 0x2001: /* mov.w Rm,@Rn */
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st_mop = MO_UW;
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break;
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case 0x2002: /* mov.l Rm,@Rn */
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st_mop = MO_UL;
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break;
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default:
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goto fail;
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}
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/* The store must match the load. */
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if (ld_adr != B11_8 || st_mop != (ld_mop & MO_SIZE)) {
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goto fail;
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}
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st_src = B7_4;
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#undef NEXT_INSN
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/*
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* Emit the operation.
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*/
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tcg_gen_insn_start(pc, ctx->envflags);
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switch (op_opc) {
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case -1:
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/* No operation found. Look for exchange pattern. */
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if (st_src == ld_dst || mv_src >= 0) {
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goto fail;
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}
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tcg_gen_atomic_xchg_i32(REG(ld_dst), REG(ld_adr), REG(st_src),
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ctx->memidx, ld_mop);
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break;
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case INDEX_op_add_i32:
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if (op_dst != st_src) {
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goto fail;
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}
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if (op_dst == ld_dst && st_mop == MO_UL) {
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tcg_gen_atomic_add_fetch_i32(REG(ld_dst), REG(ld_adr),
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op_arg, ctx->memidx, ld_mop);
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} else {
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tcg_gen_atomic_fetch_add_i32(REG(ld_dst), REG(ld_adr),
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op_arg, ctx->memidx, ld_mop);
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if (op_dst != ld_dst) {
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/* Note that mop sizes < 4 cannot use add_fetch
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because it won't carry into the higher bits. */
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tcg_gen_add_i32(REG(op_dst), REG(ld_dst), op_arg);
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}
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}
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break;
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case INDEX_op_and_i32:
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if (op_dst != st_src) {
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goto fail;
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}
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if (op_dst == ld_dst) {
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tcg_gen_atomic_and_fetch_i32(REG(ld_dst), REG(ld_adr),
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op_arg, ctx->memidx, ld_mop);
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} else {
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tcg_gen_atomic_fetch_and_i32(REG(ld_dst), REG(ld_adr),
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op_arg, ctx->memidx, ld_mop);
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tcg_gen_and_i32(REG(op_dst), REG(ld_dst), op_arg);
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}
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break;
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case INDEX_op_or_i32:
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if (op_dst != st_src) {
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goto fail;
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}
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if (op_dst == ld_dst) {
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tcg_gen_atomic_or_fetch_i32(REG(ld_dst), REG(ld_adr),
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op_arg, ctx->memidx, ld_mop);
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} else {
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tcg_gen_atomic_fetch_or_i32(REG(ld_dst), REG(ld_adr),
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op_arg, ctx->memidx, ld_mop);
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tcg_gen_or_i32(REG(op_dst), REG(ld_dst), op_arg);
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}
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break;
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case INDEX_op_xor_i32:
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if (op_dst != st_src) {
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goto fail;
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}
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if (op_dst == ld_dst) {
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tcg_gen_atomic_xor_fetch_i32(REG(ld_dst), REG(ld_adr),
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op_arg, ctx->memidx, ld_mop);
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} else {
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tcg_gen_atomic_fetch_xor_i32(REG(ld_dst), REG(ld_adr),
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op_arg, ctx->memidx, ld_mop);
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tcg_gen_xor_i32(REG(op_dst), REG(ld_dst), op_arg);
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}
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break;
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case INDEX_op_setcond_i32:
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if (st_src == ld_dst) {
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goto fail;
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}
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tcg_gen_atomic_cmpxchg_i32(REG(ld_dst), REG(ld_adr), op_arg,
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REG(st_src), ctx->memidx, ld_mop);
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tcg_gen_setcond_i32(TCG_COND_EQ, cpu_sr_t, REG(ld_dst), op_arg);
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if (mt_dst >= 0) {
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tcg_gen_mov_i32(REG(mt_dst), cpu_sr_t);
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}
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break;
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default:
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g_assert_not_reached();
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}
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/* If op_src is not a valid register, then op_arg was a constant. */
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if (op_src < 0) {
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tcg_temp_free_i32(op_arg);
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}
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/* The entire region has been translated. */
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ctx->envflags &= ~GUSA_MASK;
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ctx->pc = pc_end;
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return max_insns;
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fail:
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qemu_log_mask(LOG_UNIMP, "Unrecognized gUSA sequence %08x-%08x\n",
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pc, pc_end);
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