From d6cd3ae0ebdfab9922f932dc303e1faa618ea547 Mon Sep 17 00:00:00 2001 From: Dylan Reid Date: Fri, 6 May 2022 16:54:57 +0000 Subject: [PATCH] target/riscv: Fix VS mode hypervisor CSR access VS mode access to hypervisor CSRs should generate virtual, not illegal, instruction exceptions. Don't return early and indicate an illegal instruction exception when accessing a hypervisor CSR from VS mode. Instead, fall through to the `hmode` predicate to return the correct virtual instruction exception. Signed-off-by: Dylan Reid Reviewed-by: Alistair Francis Message-Id: <20220506165456.297058-1-dgreid@rivosinc.com> Signed-off-by: Alistair Francis --- target/riscv/csr.c | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/target/riscv/csr.c b/target/riscv/csr.c index 3500e07f92..4ea7df02c9 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -3141,13 +3141,13 @@ static inline RISCVException riscv_csrrw_check(CPURISCVState *env, #if !defined(CONFIG_USER_ONLY) int effective_priv = env->priv; - if (riscv_has_ext(env, RVH) && - env->priv == PRV_S && - !riscv_cpu_virt_enabled(env)) { + if (riscv_has_ext(env, RVH) && env->priv == PRV_S) { /* - * We are in S mode without virtualisation, therefore we are in HS Mode. + * We are in either HS or VS mode. * Add 1 to the effective privledge level to allow us to access the - * Hypervisor CSRs. + * Hypervisor CSRs. The `hmode` predicate will determine if access + * should be allowed(HS) or if a virtual instruction exception should be + * raised(VS). */ effective_priv++; }