target/mips: Clean up helper.c
Mostly fix errors and warnings reported by 'checkpatch.pl -f'. Cc: Markus Armbruster <armbru@redhat.com> Reviewed-by: Aleksandar Rikalo <aleksandar.rikalo@rt-rk.com> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com> Message-Id: <1571826227-10583-2-git-send-email-aleksandar.markovic@rt-rk.com>
This commit is contained in:
Aleksandar Markovic
parent
03bf012e52
commit
d7551ece3a
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@ -39,8 +39,8 @@ enum {
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#if !defined(CONFIG_USER_ONLY)
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/* no MMU emulation */
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int no_mmu_map_address (CPUMIPSState *env, hwaddr *physical, int *prot,
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target_ulong address, int rw, int access_type)
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int no_mmu_map_address(CPUMIPSState *env, hwaddr *physical, int *prot,
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target_ulong address, int rw, int access_type)
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{
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*physical = address;
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*prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
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@ -48,26 +48,28 @@ int no_mmu_map_address (CPUMIPSState *env, hwaddr *physical, int *prot,
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}
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/* fixed mapping MMU emulation */
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int fixed_mmu_map_address (CPUMIPSState *env, hwaddr *physical, int *prot,
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target_ulong address, int rw, int access_type)
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int fixed_mmu_map_address(CPUMIPSState *env, hwaddr *physical, int *prot,
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target_ulong address, int rw, int access_type)
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{
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if (address <= (int32_t)0x7FFFFFFFUL) {
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if (!(env->CP0_Status & (1 << CP0St_ERL)))
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if (!(env->CP0_Status & (1 << CP0St_ERL))) {
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*physical = address + 0x40000000UL;
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else
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} else {
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*physical = address;
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} else if (address <= (int32_t)0xBFFFFFFFUL)
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}
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} else if (address <= (int32_t)0xBFFFFFFFUL) {
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*physical = address & 0x1FFFFFFF;
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else
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} else {
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*physical = address;
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}
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*prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
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return TLBRET_MATCH;
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}
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/* MIPS32/MIPS64 R4000-style MMU emulation */
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int r4k_map_address (CPUMIPSState *env, hwaddr *physical, int *prot,
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target_ulong address, int rw, int access_type)
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int r4k_map_address(CPUMIPSState *env, hwaddr *physical, int *prot,
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target_ulong address, int rw, int access_type)
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{
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uint16_t ASID = env->CP0_EntryHi & env->CP0_EntryHi_ASID_mask;
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int i;
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@ -99,8 +101,9 @@ int r4k_map_address (CPUMIPSState *env, hwaddr *physical, int *prot,
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if (rw != MMU_DATA_STORE || (n ? tlb->D1 : tlb->D0)) {
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*physical = tlb->PFN[n] | (address & (mask >> 1));
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*prot = PAGE_READ;
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if (n ? tlb->D1 : tlb->D0)
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if (n ? tlb->D1 : tlb->D0) {
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*prot |= PAGE_WRITE;
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}
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if (!(n ? tlb->XI1 : tlb->XI0)) {
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*prot |= PAGE_EXEC;
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}
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@ -130,7 +133,7 @@ static int is_seg_am_mapped(unsigned int am, bool eu, int mmu_idx)
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int32_t adetlb_mask;
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switch (mmu_idx) {
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case 3 /* ERL */:
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case 3: /* ERL */
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/* If EU is set, always unmapped */
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if (eu) {
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return 0;
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@ -204,7 +207,7 @@ static int get_segctl_physical_address(CPUMIPSState *env, hwaddr *physical,
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pa & ~(hwaddr)segmask);
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}
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static int get_physical_address (CPUMIPSState *env, hwaddr *physical,
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static int get_physical_address(CPUMIPSState *env, hwaddr *physical,
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int *prot, target_ulong real_address,
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int rw, int access_type, int mmu_idx)
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{
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@ -252,14 +255,15 @@ static int get_physical_address (CPUMIPSState *env, hwaddr *physical,
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} else {
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segctl = env->CP0_SegCtl2 >> 16;
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}
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ret = get_segctl_physical_address(env, physical, prot, real_address, rw,
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access_type, mmu_idx, segctl,
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0x3FFFFFFF);
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ret = get_segctl_physical_address(env, physical, prot,
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real_address, rw, access_type,
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mmu_idx, segctl, 0x3FFFFFFF);
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#if defined(TARGET_MIPS64)
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} else if (address < 0x4000000000000000ULL) {
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/* xuseg */
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if (UX && address <= (0x3FFFFFFFFFFFFFFFULL & env->SEGMask)) {
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ret = env->tlb->map_address(env, physical, prot, real_address, rw, access_type);
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ret = env->tlb->map_address(env, physical, prot,
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real_address, rw, access_type);
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} else {
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ret = TLBRET_BADADDR;
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}
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@ -267,7 +271,8 @@ static int get_physical_address (CPUMIPSState *env, hwaddr *physical,
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/* xsseg */
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if ((supervisor_mode || kernel_mode) &&
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SX && address <= (0x7FFFFFFFFFFFFFFFULL & env->SEGMask)) {
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ret = env->tlb->map_address(env, physical, prot, real_address, rw, access_type);
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ret = env->tlb->map_address(env, physical, prot,
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real_address, rw, access_type);
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} else {
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ret = TLBRET_BADADDR;
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}
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@ -307,7 +312,8 @@ static int get_physical_address (CPUMIPSState *env, hwaddr *physical,
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/* xkseg */
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if (kernel_mode && KX &&
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address <= (0xFFFFFFFF7FFFFFFFULL & env->SEGMask)) {
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ret = env->tlb->map_address(env, physical, prot, real_address, rw, access_type);
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ret = env->tlb->map_address(env, physical, prot,
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real_address, rw, access_type);
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} else {
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ret = TLBRET_BADADDR;
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}
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@ -328,8 +334,10 @@ static int get_physical_address (CPUMIPSState *env, hwaddr *physical,
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access_type, mmu_idx,
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env->CP0_SegCtl0 >> 16, 0x1FFFFFFF);
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} else {
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/* kseg3 */
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/* XXX: debug segment is not emulated */
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/*
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* kseg3
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* XXX: debug segment is not emulated
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*/
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ret = get_segctl_physical_address(env, physical, prot, real_address, rw,
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access_type, mmu_idx,
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env->CP0_SegCtl0, 0x1FFFFFFF);
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@ -515,9 +523,9 @@ static void raise_mmu_exception(CPUMIPSState *env, target_ulong address,
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#if defined(TARGET_MIPS64)
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env->CP0_EntryHi &= env->SEGMask;
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env->CP0_XContext =
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/* PTEBase */ (env->CP0_XContext & ((~0ULL) << (env->SEGBITS - 7))) |
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/* R */ (extract64(address, 62, 2) << (env->SEGBITS - 9)) |
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/* BadVPN2 */ (extract64(address, 13, env->SEGBITS - 13) << 4);
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(env->CP0_XContext & ((~0ULL) << (env->SEGBITS - 7))) | /* PTEBase */
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(extract64(address, 62, 2) << (env->SEGBITS - 9)) | /* R */
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(extract64(address, 13, env->SEGBITS - 13) << 4); /* BadVPN2 */
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#endif
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cs->exception_index = exception;
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env->error_code = error_code;
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@ -945,7 +953,8 @@ bool mips_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
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}
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#ifndef CONFIG_USER_ONLY
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hwaddr cpu_mips_translate_address(CPUMIPSState *env, target_ulong address, int rw)
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hwaddr cpu_mips_translate_address(CPUMIPSState *env, target_ulong address,
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int rw)
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{
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hwaddr physical;
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int prot;
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@ -1005,7 +1014,7 @@ static const char * const excp_names[EXCP_LAST + 1] = {
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};
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#endif
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target_ulong exception_resume_pc (CPUMIPSState *env)
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target_ulong exception_resume_pc(CPUMIPSState *env)
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{
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target_ulong bad_pc;
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target_ulong isa_mode;
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@ -1013,8 +1022,10 @@ target_ulong exception_resume_pc (CPUMIPSState *env)
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isa_mode = !!(env->hflags & MIPS_HFLAG_M16);
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bad_pc = env->active_tc.PC | isa_mode;
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if (env->hflags & MIPS_HFLAG_BMASK) {
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/* If the exception was raised from a delay slot, come back to
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the jump. */
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/*
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* If the exception was raised from a delay slot, come back to
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* the jump.
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*/
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bad_pc -= (env->hflags & MIPS_HFLAG_B16 ? 2 : 4);
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}
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@ -1022,14 +1033,14 @@ target_ulong exception_resume_pc (CPUMIPSState *env)
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}
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#if !defined(CONFIG_USER_ONLY)
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static void set_hflags_for_handler (CPUMIPSState *env)
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static void set_hflags_for_handler(CPUMIPSState *env)
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{
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/* Exception handlers are entered in 32-bit mode. */
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env->hflags &= ~(MIPS_HFLAG_M16);
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/* ...except that microMIPS lets you choose. */
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if (env->insn_flags & ASE_MICROMIPS) {
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env->hflags |= (!!(env->CP0_Config3
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& (1 << CP0C3_ISA_ON_EXC))
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env->hflags |= (!!(env->CP0_Config3 &
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(1 << CP0C3_ISA_ON_EXC))
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<< MIPS_HFLAG_M16_SHIFT);
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}
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}
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@ -1096,10 +1107,12 @@ void mips_cpu_do_interrupt(CPUState *cs)
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switch (cs->exception_index) {
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case EXCP_DSS:
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env->CP0_Debug |= 1 << CP0DB_DSS;
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/* Debug single step cannot be raised inside a delay slot and
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resume will always occur on the next instruction
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(but we assume the pc has always been updated during
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code translation). */
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/*
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* Debug single step cannot be raised inside a delay slot and
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* resume will always occur on the next instruction
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* (but we assume the pc has always been updated during
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* code translation).
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*/
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env->CP0_DEPC = env->active_tc.PC | !!(env->hflags & MIPS_HFLAG_M16);
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goto enter_debug_mode;
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case EXCP_DINT:
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@ -1111,7 +1124,8 @@ void mips_cpu_do_interrupt(CPUState *cs)
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case EXCP_DBp:
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env->CP0_Debug |= 1 << CP0DB_DBp;
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/* Setup DExcCode - SDBBP instruction */
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env->CP0_Debug = (env->CP0_Debug & ~(0x1fULL << CP0DB_DEC)) | 9 << CP0DB_DEC;
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env->CP0_Debug = (env->CP0_Debug & ~(0x1fULL << CP0DB_DEC)) |
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(9 << CP0DB_DEC);
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goto set_DEPC;
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case EXCP_DDBS:
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env->CP0_Debug |= 1 << CP0DB_DDBS;
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@ -1132,8 +1146,9 @@ void mips_cpu_do_interrupt(CPUState *cs)
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env->hflags |= MIPS_HFLAG_DM | MIPS_HFLAG_CP0;
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env->hflags &= ~(MIPS_HFLAG_KSU);
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/* EJTAG probe trap enable is not implemented... */
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if (!(env->CP0_Status & (1 << CP0St_EXL)))
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if (!(env->CP0_Status & (1 << CP0St_EXL))) {
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env->CP0_Cause &= ~(1U << CP0Ca_BD);
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}
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env->active_tc.PC = env->exception_base + 0x480;
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set_hflags_for_handler(env);
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break;
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@ -1159,8 +1174,9 @@ void mips_cpu_do_interrupt(CPUState *cs)
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}
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env->hflags |= MIPS_HFLAG_CP0;
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env->hflags &= ~(MIPS_HFLAG_KSU);
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if (!(env->CP0_Status & (1 << CP0St_EXL)))
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if (!(env->CP0_Status & (1 << CP0St_EXL))) {
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env->CP0_Cause &= ~(1U << CP0Ca_BD);
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}
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env->active_tc.PC = env->exception_base;
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set_hflags_for_handler(env);
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break;
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@ -1176,12 +1192,16 @@ void mips_cpu_do_interrupt(CPUState *cs)
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uint32_t pending = (env->CP0_Cause & CP0Ca_IP_mask) >> CP0Ca_IP;
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if (env->CP0_Config3 & (1 << CP0C3_VEIC)) {
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/* For VEIC mode, the external interrupt controller feeds
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* the vector through the CP0Cause IP lines. */
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/*
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* For VEIC mode, the external interrupt controller feeds
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* the vector through the CP0Cause IP lines.
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*/
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vector = pending;
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} else {
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/* Vectored Interrupts
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* Mask with Status.IM7-IM0 to get enabled interrupts. */
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/*
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* Vectored Interrupts
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* Mask with Status.IM7-IM0 to get enabled interrupts.
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*/
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pending &= (env->CP0_Status >> CP0St_IM) & 0xff;
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/* Find the highest-priority interrupt. */
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while (pending >>= 1) {
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@ -1354,7 +1374,8 @@ void mips_cpu_do_interrupt(CPUState *cs)
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env->active_tc.PC += offset;
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set_hflags_for_handler(env);
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env->CP0_Cause = (env->CP0_Cause & ~(0x1f << CP0Ca_EC)) | (cause << CP0Ca_EC);
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env->CP0_Cause = (env->CP0_Cause & ~(0x1f << CP0Ca_EC)) |
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(cause << CP0Ca_EC);
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break;
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default:
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abort();
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@ -1390,7 +1411,7 @@ bool mips_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
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}
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#if !defined(CONFIG_USER_ONLY)
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void r4k_invalidate_tlb (CPUMIPSState *env, int idx, int use_extra)
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void r4k_invalidate_tlb(CPUMIPSState *env, int idx, int use_extra)
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{
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CPUState *cs = env_cpu(env);
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r4k_tlb_t *tlb;
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@ -1400,16 +1421,20 @@ void r4k_invalidate_tlb (CPUMIPSState *env, int idx, int use_extra)
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target_ulong mask;
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tlb = &env->tlb->mmu.r4k.tlb[idx];
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/* The qemu TLB is flushed when the ASID changes, so no need to
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flush these entries again. */
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/*
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* The qemu TLB is flushed when the ASID changes, so no need to
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* flush these entries again.
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*/
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if (tlb->G == 0 && tlb->ASID != ASID) {
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return;
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}
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if (use_extra && env->tlb->tlb_in_use < MIPS_TLB_MAX) {
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/* For tlbwr, we can shadow the discarded entry into
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a new (fake) TLB entry, as long as the guest can not
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tell that it's there. */
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/*
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* For tlbwr, we can shadow the discarded entry into
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* a new (fake) TLB entry, as long as the guest can not
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* tell that it's there.
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*/
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env->tlb->mmu.r4k.tlb[env->tlb->tlb_in_use] = *tlb;
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env->tlb->tlb_in_use++;
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return;
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