More phys_ram_base elimination.
Signed-off-by: Paul Brook <paul@codesourcery.com> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@7064 c046a42c-6fe2-441c-8c8c-71466251a162
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pbrook
parent
b584726df9
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d758525180
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@ -521,33 +521,34 @@ static void network_init (PCIBus *pci_bus)
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a3 - RAM size in bytes
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*/
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static void write_bootloader (CPUState *env, unsigned long bios_offset, int64_t kernel_entry)
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static void write_bootloader (CPUState *env, uint8_t *base,
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int64_t kernel_entry)
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{
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uint32_t *p;
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/* Small bootloader */
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p = (uint32_t *) (phys_ram_base + bios_offset);
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p = (uint32_t *)base;
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stl_raw(p++, 0x0bf00160); /* j 0x1fc00580 */
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stl_raw(p++, 0x00000000); /* nop */
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/* YAMON service vector */
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stl_raw(phys_ram_base + bios_offset + 0x500, 0xbfc00580); /* start: */
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stl_raw(phys_ram_base + bios_offset + 0x504, 0xbfc0083c); /* print_count: */
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stl_raw(phys_ram_base + bios_offset + 0x520, 0xbfc00580); /* start: */
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stl_raw(phys_ram_base + bios_offset + 0x52c, 0xbfc00800); /* flush_cache: */
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stl_raw(phys_ram_base + bios_offset + 0x534, 0xbfc00808); /* print: */
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stl_raw(phys_ram_base + bios_offset + 0x538, 0xbfc00800); /* reg_cpu_isr: */
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stl_raw(phys_ram_base + bios_offset + 0x53c, 0xbfc00800); /* unred_cpu_isr: */
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stl_raw(phys_ram_base + bios_offset + 0x540, 0xbfc00800); /* reg_ic_isr: */
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stl_raw(phys_ram_base + bios_offset + 0x544, 0xbfc00800); /* unred_ic_isr: */
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stl_raw(phys_ram_base + bios_offset + 0x548, 0xbfc00800); /* reg_esr: */
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stl_raw(phys_ram_base + bios_offset + 0x54c, 0xbfc00800); /* unreg_esr: */
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stl_raw(phys_ram_base + bios_offset + 0x550, 0xbfc00800); /* getchar: */
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stl_raw(phys_ram_base + bios_offset + 0x554, 0xbfc00800); /* syscon_read: */
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stl_raw(base + 0x500, 0xbfc00580); /* start: */
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stl_raw(base + 0x504, 0xbfc0083c); /* print_count: */
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stl_raw(base + 0x520, 0xbfc00580); /* start: */
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stl_raw(base + 0x52c, 0xbfc00800); /* flush_cache: */
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stl_raw(base + 0x534, 0xbfc00808); /* print: */
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stl_raw(base + 0x538, 0xbfc00800); /* reg_cpu_isr: */
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stl_raw(base + 0x53c, 0xbfc00800); /* unred_cpu_isr: */
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stl_raw(base + 0x540, 0xbfc00800); /* reg_ic_isr: */
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stl_raw(base + 0x544, 0xbfc00800); /* unred_ic_isr: */
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stl_raw(base + 0x548, 0xbfc00800); /* reg_esr: */
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stl_raw(base + 0x54c, 0xbfc00800); /* unreg_esr: */
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stl_raw(base + 0x550, 0xbfc00800); /* getchar: */
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stl_raw(base + 0x554, 0xbfc00800); /* syscon_read: */
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/* Second part of the bootloader */
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p = (uint32_t *) (phys_ram_base + bios_offset + 0x580);
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p = (uint32_t *) (base + 0x580);
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stl_raw(p++, 0x24040002); /* addiu a0, zero, 2 */
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stl_raw(p++, 0x3c1d0000 | (((ENVP_ADDR - 64) >> 16) & 0xffff)); /* lui sp, high(ENVP_ADDR) */
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stl_raw(p++, 0x37bd0000 | ((ENVP_ADDR - 64) & 0xffff)); /* ori sp, sp, low(ENVP_ADDR) */
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@ -616,7 +617,7 @@ static void write_bootloader (CPUState *env, unsigned long bios_offset, int64_t
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stl_raw(p++, 0x00000000); /* nop */
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/* YAMON subroutines */
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p = (uint32_t *) (phys_ram_base + bios_offset + 0x800);
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p = (uint32_t *) (base + 0x800);
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stl_raw(p++, 0x03e00008); /* jr ra */
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stl_raw(p++, 0x24020000); /* li v0,0 */
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/* 808 YAMON print */
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@ -662,30 +663,29 @@ static void write_bootloader (CPUState *env, unsigned long bios_offset, int64_t
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static void prom_set(int index, const char *string, ...)
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{
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char buf[ENVP_ENTRY_SIZE];
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target_phys_addr_t p;
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va_list ap;
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int32_t *p;
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int32_t table_addr;
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char *s;
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if (index >= ENVP_NB_ENTRIES)
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return;
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p = (int32_t *) (phys_ram_base + ENVP_ADDR + VIRT_TO_PHYS_ADDEND);
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p += index;
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p = ENVP_ADDR + VIRT_TO_PHYS_ADDEND + index * 4;
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if (string == NULL) {
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stl_raw(p, 0);
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stl_phys(p, 0);
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return;
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}
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table_addr = ENVP_ADDR + sizeof(int32_t) * ENVP_NB_ENTRIES + index * ENVP_ENTRY_SIZE;
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s = (char *) (phys_ram_base + VIRT_TO_PHYS_ADDEND + table_addr);
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table_addr = ENVP_ADDR + sizeof(int32_t) * ENVP_NB_ENTRIES
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+ index * ENVP_ENTRY_SIZE + VIRT_TO_PHYS_ADDEND;
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stl_raw(p, table_addr);
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va_start(ap, string);
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vsnprintf (s, ENVP_ENTRY_SIZE, string, ap);
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vsnprintf(buf, ENVP_ENTRY_SIZE, string, ap);
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va_end(ap);
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pstrcpy_targphys(table_addr, ENVP_ENTRY_SIZE, buf);
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}
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/* Kernel */
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@ -834,7 +834,7 @@ void mips_malta_init (ram_addr_t ram_size, int vga_ram_size,
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loaderparams.initrd_filename = initrd_filename;
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kernel_entry = load_kernel(env);
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env->CP0_Status &= ~((1 << CP0St_BEV) | (1 << CP0St_ERL));
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write_bootloader(env, bios_offset, kernel_entry);
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write_bootloader(env, qemu_get_ram_ptr(bios_offset), kernel_entry);
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} else {
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index = drive_get_index(IF_PFLASH, 0, fl_idx);
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if (index != -1) {
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@ -868,11 +868,10 @@ void mips_malta_init (ram_addr_t ram_size, int vga_ram_size,
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a neat trick which allows bi-endian firmware. */
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#ifndef TARGET_WORDS_BIGENDIAN
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{
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uint32_t *addr;
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for (addr = (uint32_t *)(phys_ram_base + bios_offset);
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addr < (uint32_t *)(phys_ram_base + bios_offset + bios_size);
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addr++) {
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*addr = bswap32(*addr);
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uint32_t *addr = qemu_get_ram_ptr(bios_offset);;
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uint32_t *end = addr + bios_size;
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while (addr < end) {
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bswap32s(addr);
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}
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}
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#endif
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@ -881,7 +880,7 @@ void mips_malta_init (ram_addr_t ram_size, int vga_ram_size,
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/* Board ID = 0x420 (Malta Board with CoreLV)
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XXX: theoretically 0x1e000010 should map to flash and 0x1fc00010 should
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map to the board ID. */
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stl_raw(phys_ram_base + bios_offset + 0x10, 0x00000420);
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stl_phys(0x1fc00010LL, 0x00000420);
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/* Init internal devices */
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cpu_mips_irq_init_cpu(env);
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@ -80,6 +80,7 @@ static void load_kernel (CPUState *env)
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int64_t entry, kernel_low, kernel_high;
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long kernel_size, initrd_size;
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ram_addr_t initrd_offset;
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int ret;
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kernel_size = load_elf(loaderparams.kernel_filename, VIRT_TO_PHYS_ADDEND,
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(uint64_t *)&entry, (uint64_t *)&kernel_low,
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@ -120,21 +121,19 @@ static void load_kernel (CPUState *env)
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/* Store command line. */
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if (initrd_size > 0) {
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int ret;
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ret = sprintf((char *)(phys_ram_base + (16 << 20) - 256),
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"rd_start=0x" TARGET_FMT_lx " rd_size=%li ",
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PHYS_TO_VIRT((uint32_t)initrd_offset),
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initrd_size);
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strcpy ((char *)(phys_ram_base + (16 << 20) - 256 + ret),
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loaderparams.kernel_cmdline);
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}
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else {
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strcpy ((char *)(phys_ram_base + (16 << 20) - 256),
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loaderparams.kernel_cmdline);
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char buf[64];
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ret = snprintf(buf, 64, "rd_start=0x" TARGET_FMT_lx " rd_size=%li ",
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PHYS_TO_VIRT((uint32_t)initrd_offset),
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initrd_size);
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cpu_physical_memory_write((16 << 20) - 256, (void *)buf, 64);
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} else {
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ret = 0;
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}
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pstrcpy_targphys((16 << 20) - 256 + ret, 256,
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loaderparams.kernel_cmdline);
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*(int32_t *)(phys_ram_base + (16 << 20) - 260) = tswap32 (0x12345678);
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*(int32_t *)(phys_ram_base + (16 << 20) - 264) = tswap32 (ram_size);
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stl_phys((16 << 20) - 260, 0x12345678);
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stl_phys((16 << 20) - 264, ram_size);
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}
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static void main_cpu_reset(void *opaque)
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@ -182,7 +182,7 @@ static void mpc8544ds_init(ram_addr_t ram_size, int vga_ram_size,
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ram_size &= ~(RAM_SIZES_ALIGN - 1);
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/* Register Memory */
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cpu_register_physical_memory(0, ram_size, 0);
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cpu_register_physical_memory(0, ram_size, qemu_ram_alloc(ram_size));
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/* MPIC */
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irqs = qemu_mallocz(sizeof(qemu_irq) * OPENPIC_OUTPUT_NB);
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@ -247,7 +247,8 @@ static void mpc8544ds_init(ram_addr_t ram_size, int vga_ram_size,
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/* Load initrd. */
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if (initrd_filename) {
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initrd_size = load_image(initrd_filename, phys_ram_base + initrd_base);
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initrd_size = load_image_targphys(initrd_filename, initrd_base,
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ram_size - initrd_base);
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if (initrd_size < 0) {
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fprintf(stderr, "qemu: could not load initial ram disk '%s'\n",
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@ -283,12 +283,11 @@ static inline void pxa2xx_dma_rdst_set(struct pxa2xx_lcdc_s *s)
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/* Load new Frame Descriptors from DMA */
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static void pxa2xx_descriptor_load(struct pxa2xx_lcdc_s *s)
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{
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struct pxa_frame_descriptor_s *desc[PXA_LCDDMA_CHANS];
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struct pxa_frame_descriptor_s desc;
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target_phys_addr_t descptr;
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int i;
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for (i = 0; i < PXA_LCDDMA_CHANS; i ++) {
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desc[i] = 0;
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s->dma_ch[i].source = 0;
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if (!s->dma_ch[i].up)
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@ -303,15 +302,14 @@ static void pxa2xx_descriptor_load(struct pxa2xx_lcdc_s *s)
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descptr = s->dma_ch[i].descriptor;
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if (!(descptr >= PXA2XX_SDRAM_BASE && descptr +
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sizeof(*desc[i]) <= PXA2XX_SDRAM_BASE + phys_ram_size))
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sizeof(desc) <= PXA2XX_SDRAM_BASE + phys_ram_size))
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continue;
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descptr -= PXA2XX_SDRAM_BASE;
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desc[i] = (struct pxa_frame_descriptor_s *) (phys_ram_base + descptr);
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s->dma_ch[i].descriptor = desc[i]->fdaddr;
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s->dma_ch[i].source = desc[i]->fsaddr;
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s->dma_ch[i].id = desc[i]->fidr;
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s->dma_ch[i].command = desc[i]->ldcmd;
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cpu_physical_memory_read(descptr, (void *)&desc, sizeof(desc));
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s->dma_ch[i].descriptor = tswap32(desc.fdaddr);
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s->dma_ch[i].source = tswap32(desc.fsaddr);
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s->dma_ch[i].id = tswap32(desc.fidr);
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s->dma_ch[i].command = tswap32(desc.ldcmd);
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}
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}
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