dma/rc4030: convert to QOM
Signed-off-by: Hervé Poussineau <hpoussin@reactos.org> Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Leon Alrae <leon.alrae@imgtec.com>
This commit is contained in:
Hervé Poussineau
Leon Alrae
parent
95c357bc46
commit
d791d60f1c
119
hw/dma/rc4030.c
119
hw/dma/rc4030.c
@ -1,7 +1,7 @@
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/*
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* QEMU JAZZ RC4030 chipset
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*
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* Copyright (c) 2007-2009 Herve Poussineau
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* Copyright (c) 2007-2013 Hervé Poussineau
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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@ -24,6 +24,7 @@
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#include "hw/hw.h"
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#include "hw/mips/mips.h"
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#include "hw/sysbus.h"
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#include "qemu/timer.h"
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#include "exec/address-spaces.h"
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#include "trace.h"
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@ -49,8 +50,14 @@ typedef struct dma_pagetable_entry {
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#define DMA_FLAG_MEM_INTR 0x0200
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#define DMA_FLAG_ADDR_INTR 0x0400
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#define TYPE_RC4030 "rc4030"
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#define RC4030(obj) \
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OBJECT_CHECK(rc4030State, (obj), TYPE_RC4030)
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typedef struct rc4030State
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{
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SysBusDevice parent;
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uint32_t config; /* 0x0000: RC4030 config register */
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uint32_t revision; /* 0x0008: RC4030 Revision register */
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uint32_t invalid_address_register; /* 0x0010: Invalid Address register */
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@ -317,7 +324,7 @@ static void rc4030_dma_tt_update(rc4030State *s, uint32_t new_tl_base,
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} else {
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dma_tt_size = memory_region_size(&s->dma_tt);
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}
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memory_region_init_alias(&s->dma_tt_alias, NULL,
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memory_region_init_alias(&s->dma_tt_alias, OBJECT(s),
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"dma-table-alias",
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&s->dma_tt, 0, dma_tt_size);
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dma_tl_contents = memory_region_get_ram_ptr(&s->dma_tt);
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@ -332,7 +339,7 @@ static void rc4030_dma_tt_update(rc4030State *s, uint32_t new_tl_base,
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&s->dma_tt_alias);
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memory_region_transaction_commit();
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} else {
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memory_region_init(&s->dma_tt_alias, NULL,
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memory_region_init(&s->dma_tt_alias, OBJECT(s),
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"dma-table-alias", 0);
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}
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}
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@ -577,9 +584,9 @@ static const MemoryRegionOps jazzio_ops = {
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.endianness = DEVICE_NATIVE_ENDIAN,
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};
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static void rc4030_reset(void *opaque)
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static void rc4030_reset(DeviceState *dev)
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{
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rc4030State *s = opaque;
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rc4030State *s = RC4030(dev);
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int i;
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s->config = 0x410; /* some boards seem to accept 0x104 too */
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@ -733,46 +740,102 @@ static rc4030_dma *rc4030_allocate_dmas(void *opaque, int n)
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return s;
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}
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MemoryRegion *rc4030_init(qemu_irq timer, qemu_irq jazz_bus,
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qemu_irq **irqs, rc4030_dma **dmas,
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MemoryRegion *sysmem)
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static void rc4030_initfn(Object *obj)
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{
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rc4030State *s;
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DeviceState *dev = DEVICE(obj);
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rc4030State *s = RC4030(obj);
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SysBusDevice *sysbus = SYS_BUS_DEVICE(obj);
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qdev_init_gpio_in(dev, rc4030_irq_jazz_request, 16);
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sysbus_init_irq(sysbus, &s->timer_irq);
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sysbus_init_irq(sysbus, &s->jazz_bus_irq);
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register_savevm(NULL, "rc4030", 0, 2, rc4030_save, rc4030_load, s);
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sysbus_init_mmio(sysbus, &s->iomem_chipset);
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sysbus_init_mmio(sysbus, &s->iomem_jazzio);
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}
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static void rc4030_realize(DeviceState *dev, Error **errp)
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{
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rc4030State *s = RC4030(dev);
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Object *o = OBJECT(dev);
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int i;
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s = g_malloc0(sizeof(rc4030State));
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*irqs = qemu_allocate_irqs(rc4030_irq_jazz_request, s, 16);
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*dmas = rc4030_allocate_dmas(s, 4);
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s->periodic_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, rc4030_periodic_timer, s);
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s->timer_irq = timer;
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s->jazz_bus_irq = jazz_bus;
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qemu_register_reset(rc4030_reset, s);
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register_savevm(NULL, "rc4030", 0, 2, rc4030_save, rc4030_load, s);
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rc4030_reset(s);
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s->periodic_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL,
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rc4030_periodic_timer, s);
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memory_region_init_io(&s->iomem_chipset, NULL, &rc4030_ops, s,
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"rc4030.chipset", 0x300);
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memory_region_add_subregion(sysmem, 0x80000000, &s->iomem_chipset);
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memory_region_init_io(&s->iomem_jazzio, NULL, &jazzio_ops, s,
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"rc4030.jazzio", 0x00001000);
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memory_region_add_subregion(sysmem, 0xf0000000, &s->iomem_jazzio);
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memory_region_init_rom_device(&s->dma_tt, NULL,
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memory_region_init_rom_device(&s->dma_tt, o,
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&rc4030_dma_tt_ops, s, "dma-table",
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MAX_TL_ENTRIES * sizeof(dma_pagetable_entry),
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NULL);
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memory_region_init(&s->dma_tt_alias, NULL, "dma-table-alias", 0);
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memory_region_init(&s->dma_mr, NULL, "dma", INT32_MAX);
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memory_region_init(&s->dma_tt_alias, o, "dma-table-alias", 0);
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memory_region_init(&s->dma_mr, o, "dma", INT32_MAX);
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for (i = 0; i < MAX_TL_ENTRIES; ++i) {
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memory_region_init_alias(&s->dma_mrs[i], NULL, "dma-alias",
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memory_region_init_alias(&s->dma_mrs[i], o, "dma-alias",
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get_system_memory(), 0, DMA_PAGESIZE);
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memory_region_set_enabled(&s->dma_mrs[i], false);
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memory_region_add_subregion(&s->dma_mr, i * DMA_PAGESIZE,
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&s->dma_mrs[i]);
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}
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address_space_init(&s->dma_as, &s->dma_mr, "rc4030-dma");
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return &s->dma_mr;
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}
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static void rc4030_unrealize(DeviceState *dev, Error **errp)
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{
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rc4030State *s = RC4030(dev);
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int i;
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timer_free(s->periodic_timer);
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address_space_destroy(&s->dma_as);
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object_unparent(OBJECT(&s->dma_tt));
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object_unparent(OBJECT(&s->dma_tt_alias));
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object_unparent(OBJECT(&s->dma_mr));
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for (i = 0; i < MAX_TL_ENTRIES; ++i) {
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memory_region_del_subregion(&s->dma_mr, &s->dma_mrs[i]);
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object_unparent(OBJECT(&s->dma_mrs[i]));
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}
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}
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static void rc4030_class_init(ObjectClass *klass, void *class_data)
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{
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DeviceClass *dc = DEVICE_CLASS(klass);
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dc->realize = rc4030_realize;
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dc->unrealize = rc4030_unrealize;
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dc->reset = rc4030_reset;
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}
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static const TypeInfo rc4030_info = {
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.name = TYPE_RC4030,
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.parent = TYPE_SYS_BUS_DEVICE,
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.instance_size = sizeof(rc4030State),
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.instance_init = rc4030_initfn,
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.class_init = rc4030_class_init,
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};
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static void rc4030_register_types(void)
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{
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type_register_static(&rc4030_info);
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}
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type_init(rc4030_register_types)
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DeviceState *rc4030_init(rc4030_dma **dmas, MemoryRegion **dma_mr)
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{
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DeviceState *dev;
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dev = qdev_create(NULL, TYPE_RC4030);
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qdev_init_nofail(dev);
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*dmas = rc4030_allocate_dmas(dev, 4);
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*dma_mr = &RC4030(dev)->dma_mr;
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return dev;
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}
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@ -135,7 +135,7 @@ static void mips_jazz_init(MachineState *machine,
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MIPSCPU *cpu;
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CPUClass *cc;
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CPUMIPSState *env;
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qemu_irq *rc4030, *i8259;
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qemu_irq *i8259;
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rc4030_dma *dmas;
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MemoryRegion *rc4030_dma_mr;
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MemoryRegion *isa_mem = g_new(MemoryRegion, 1);
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@ -144,7 +144,7 @@ static void mips_jazz_init(MachineState *machine,
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MemoryRegion *i8042 = g_new(MemoryRegion, 1);
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MemoryRegion *dma_dummy = g_new(MemoryRegion, 1);
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NICInfo *nd;
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DeviceState *dev;
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DeviceState *dev, *rc4030;
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SysBusDevice *sysbus;
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ISABus *isa_bus;
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ISADevice *pit;
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@ -213,8 +213,14 @@ static void mips_jazz_init(MachineState *machine,
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cpu_mips_clock_init(env);
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/* Chipset */
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rc4030_dma_mr = rc4030_init(env->irq[6], env->irq[3], &rc4030, &dmas,
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address_space);
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rc4030 = rc4030_init(&dmas, &rc4030_dma_mr);
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sysbus = SYS_BUS_DEVICE(rc4030);
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sysbus_connect_irq(sysbus, 0, env->irq[6]);
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sysbus_connect_irq(sysbus, 1, env->irq[3]);
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memory_region_add_subregion(address_space, 0x80000000,
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sysbus_mmio_get_region(sysbus, 0));
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memory_region_add_subregion(address_space, 0xf0000000,
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sysbus_mmio_get_region(sysbus, 1));
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memory_region_init_io(dma_dummy, NULL, &dma_dummy_ops, NULL, "dummy_dma", 0x1000);
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memory_region_add_subregion(address_space, 0x8000d000, dma_dummy);
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@ -241,7 +247,7 @@ static void mips_jazz_init(MachineState *machine,
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sysbus = SYS_BUS_DEVICE(dev);
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sysbus_mmio_map(sysbus, 0, 0x60080000);
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sysbus_mmio_map(sysbus, 1, 0x40000000);
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sysbus_connect_irq(sysbus, 0, rc4030[3]);
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sysbus_connect_irq(sysbus, 0, qdev_get_gpio_in(rc4030, 3));
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{
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/* Simple ROM, so user doesn't have to provide one */
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MemoryRegion *rom_mr = g_new(MemoryRegion, 1);
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@ -267,8 +273,8 @@ static void mips_jazz_init(MachineState *machine,
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if (!nd->model)
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nd->model = g_strdup("dp83932");
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if (strcmp(nd->model, "dp83932") == 0) {
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dp83932_init(nd, 0x80001000, 2, get_system_memory(), rc4030[4],
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rc4030_dma_mr);
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dp83932_init(nd, 0x80001000, 2, get_system_memory(),
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qdev_get_gpio_in(rc4030, 4), rc4030_dma_mr);
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break;
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} else if (is_help_option(nd->model)) {
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fprintf(stderr, "qemu: Supported NICs: dp83932\n");
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@ -282,7 +288,7 @@ static void mips_jazz_init(MachineState *machine,
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/* SCSI adapter */
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esp_init(0x80002000, 0,
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rc4030_dma_read, rc4030_dma_write, dmas[0],
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rc4030[5], &esp_reset, &dma_enable);
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qdev_get_gpio_in(rc4030, 5), &esp_reset, &dma_enable);
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/* Floppy */
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if (drive_get_max_bus(IF_FLOPPY) >= MAX_FD) {
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@ -292,7 +298,7 @@ static void mips_jazz_init(MachineState *machine,
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for (n = 0; n < MAX_FD; n++) {
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fds[n] = drive_get(IF_FLOPPY, 0, n);
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}
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fdctrl_init_sysbus(rc4030[1], 0, 0x80003000, fds);
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fdctrl_init_sysbus(qdev_get_gpio_in(rc4030, 1), 0, 0x80003000, fds);
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/* Real time clock */
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rtc_init(isa_bus, 1980, NULL);
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@ -300,23 +306,26 @@ static void mips_jazz_init(MachineState *machine,
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memory_region_add_subregion(address_space, 0x80004000, rtc);
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/* Keyboard (i8042) */
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i8042_mm_init(rc4030[6], rc4030[7], i8042, 0x1000, 0x1);
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i8042_mm_init(qdev_get_gpio_in(rc4030, 6), qdev_get_gpio_in(rc4030, 7),
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i8042, 0x1000, 0x1);
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memory_region_add_subregion(address_space, 0x80005000, i8042);
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/* Serial ports */
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if (serial_hds[0]) {
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serial_mm_init(address_space, 0x80006000, 0, rc4030[8], 8000000/16,
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serial_mm_init(address_space, 0x80006000, 0,
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qdev_get_gpio_in(rc4030, 8), 8000000/16,
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serial_hds[0], DEVICE_NATIVE_ENDIAN);
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}
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if (serial_hds[1]) {
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serial_mm_init(address_space, 0x80007000, 0, rc4030[9], 8000000/16,
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serial_mm_init(address_space, 0x80007000, 0,
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qdev_get_gpio_in(rc4030, 9), 8000000/16,
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serial_hds[1], DEVICE_NATIVE_ENDIAN);
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}
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/* Parallel port */
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if (parallel_hds[0])
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parallel_mm_init(address_space, 0x80008000, 0, rc4030[0],
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parallel_hds[0]);
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parallel_mm_init(address_space, 0x80008000, 0,
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qdev_get_gpio_in(rc4030, 0), parallel_hds[0]);
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/* FIXME: missing Jazz sound at 0x8000c000, rc4030[2] */
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@ -18,9 +18,7 @@ typedef struct rc4030DMAState *rc4030_dma;
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void rc4030_dma_read(void *dma, uint8_t *buf, int len);
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void rc4030_dma_write(void *dma, uint8_t *buf, int len);
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MemoryRegion *rc4030_init(qemu_irq timer, qemu_irq jazz_bus,
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qemu_irq **irqs, rc4030_dma **dmas,
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MemoryRegion *sysmem);
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DeviceState *rc4030_init(rc4030_dma **dmas, MemoryRegion **dma_mr);
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/* dp8393x.c */
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void dp83932_init(NICInfo *nd, hwaddr base, int it_shift,
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