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target/i386: isolate MMX code more

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Extracted from a patch by Paul Brook <paul@nowt.org>.

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
This commit is contained in:
Paolo Bonzini 2022-08-27 00:44:38 +02:00
parent 2607e76ffd
commit d7a851f89a
1 changed files with 33 additions and 19 deletions
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52
target/i386/tcg/translate.c
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@ -3888,6 +3888,12 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,
gen_ldo_env_A0(s, op2_offset); gen_ldo_env_A0(s, op2_offset);
} }
} }
if (!op6->op[b1]) {
goto illegal_op;
}
tcg_gen_addi_ptr(s->ptr0, cpu_env, op1_offset);
tcg_gen_addi_ptr(s->ptr1, cpu_env, op2_offset);
op6->op[b1](cpu_env, s->ptr0, s->ptr1);
} else { } else {
if ((op6->flags & SSE_OPF_MMX) == 0) { if ((op6->flags & SSE_OPF_MMX) == 0) {
goto unknown_op; goto unknown_op;
@ -3900,14 +3906,10 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,
gen_lea_modrm(env, s, modrm); gen_lea_modrm(env, s, modrm);
gen_ldq_env_A0(s, op2_offset); gen_ldq_env_A0(s, op2_offset);
} }
tcg_gen_addi_ptr(s->ptr0, cpu_env, op1_offset);
tcg_gen_addi_ptr(s->ptr1, cpu_env, op2_offset);
op6->op[0](cpu_env, s->ptr0, s->ptr1);
} }
if (!op6->op[b1]) {
goto illegal_op;
}
tcg_gen_addi_ptr(s->ptr0, cpu_env, op1_offset);
tcg_gen_addi_ptr(s->ptr1, cpu_env, op2_offset);
op6->op[b1](cpu_env, s->ptr0, s->ptr1);
if (op6->flags & SSE_OPF_CMP) { if (op6->flags & SSE_OPF_CMP) {
set_cc_op(s, CC_OP_EFLAGS); set_cc_op(s, CC_OP_EFLAGS);
@ -4427,16 +4429,8 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,
return; return;
} }
if (b1) { if (b1 == 0) {
op1_offset = ZMM_OFFSET(reg); /* MMX */
if (mod == 3) {
op2_offset = ZMM_OFFSET(rm | REX_B(s));
} else {
op2_offset = offsetof(CPUX86State,xmm_t0);
gen_lea_modrm(env, s, modrm);
gen_ldo_env_A0(s, op2_offset);
}
} else {
if ((op7->flags & SSE_OPF_MMX) == 0) { if ((op7->flags & SSE_OPF_MMX) == 0) {
goto illegal_op; goto illegal_op;
} }
@ -4448,9 +4442,29 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,
gen_lea_modrm(env, s, modrm); gen_lea_modrm(env, s, modrm);
gen_ldq_env_A0(s, op2_offset); gen_ldq_env_A0(s, op2_offset);
} }
} val = x86_ldub_code(env, s);
val = x86_ldub_code(env, s); tcg_gen_addi_ptr(s->ptr0, cpu_env, op1_offset);
tcg_gen_addi_ptr(s->ptr1, cpu_env, op2_offset);
/* We only actually have one MMX instuction (palignr) */
assert(b == 0x0f);
op7->op[0](cpu_env, s->ptr0, s->ptr1,
tcg_const_i32(val));
break;
}
/* SSE */
op1_offset = ZMM_OFFSET(reg);
if (mod == 3) {
op2_offset = ZMM_OFFSET(rm | REX_B(s));
} else {
op2_offset = offsetof(CPUX86State, xmm_t0);
gen_lea_modrm(env, s, modrm);
gen_ldo_env_A0(s, op2_offset);
}
val = x86_ldub_code(env, s);
if ((b & 0xfc) == 0x60) { /* pcmpXstrX */ if ((b & 0xfc) == 0x60) { /* pcmpXstrX */
set_cc_op(s, CC_OP_EFLAGS); set_cc_op(s, CC_OP_EFLAGS);