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target/arm/cpu.h: add additional float_status flags

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Half-precision flush to zero behaviour is controlled by a separate
FZ16 bit in the FPCR. To handle this we pass a pointer to
fp_status_fp16 when working on half-precision operations. The value of
the presented FPCR is calculated from an amalgam of the two when read.

Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20180227143852.11175-5-alex.bennee@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Alex Bennée 2018-03-01 11:05:47 +00:00 committed by Peter Maydell
parent d0e69ea88f
commit d81ce0ef2c
3 changed files with 75 additions and 36 deletions
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32
target/arm/cpu.h
View File

@ -538,19 +538,29 @@ typedef struct CPUARMState {
/* scratch space when Tn are not sufficient. */ /* scratch space when Tn are not sufficient. */
uint32_t scratch[8]; uint32_t scratch[8];
/* fp_status is the "normal" fp status. standard_fp_status retains /* There are a number of distinct float control structures:
* values corresponding to the ARM "Standard FPSCR Value", ie *
* default-NaN, flush-to-zero, round-to-nearest and is used by * fp_status: is the "normal" fp status.
* any operations (generally Neon) which the architecture defines * fp_status_fp16: used for half-precision calculations
* as controlled by the standard FPSCR value rather than the FPSCR. * standard_fp_status : the ARM "Standard FPSCR Value"
*
* Half-precision operations are governed by a separate
* flush-to-zero control bit in FPSCR:FZ16. We pass a separate
* status structure to control this.
*
* The "Standard FPSCR", ie default-NaN, flush-to-zero,
* round-to-nearest and is used by any operations (generally
* Neon) which the architecture defines as controlled by the
* standard FPSCR value rather than the FPSCR.
* *
* To avoid having to transfer exception bits around, we simply * To avoid having to transfer exception bits around, we simply
* say that the FPSCR cumulative exception flags are the logical * say that the FPSCR cumulative exception flags are the logical
* OR of the flags in the two fp statuses. This relies on the * OR of the flags in the three fp statuses. This relies on the
* only thing which needs to read the exception flags being * only thing which needs to read the exception flags being
* an explicit FPSCR read. * an explicit FPSCR read.
*/ */
float_status fp_status; float_status fp_status;
float_status fp_status_f16;
float_status standard_fp_status; float_status standard_fp_status;
/* ZCR_EL[1-3] */ /* ZCR_EL[1-3] */
@ -1190,12 +1200,20 @@ static inline void xpsr_write(CPUARMState *env, uint32_t val, uint32_t mask)
uint32_t vfp_get_fpscr(CPUARMState *env); uint32_t vfp_get_fpscr(CPUARMState *env);
void vfp_set_fpscr(CPUARMState *env, uint32_t val); void vfp_set_fpscr(CPUARMState *env, uint32_t val);
/* For A64 the FPSCR is split into two logically distinct registers, /* FPCR, Floating Point Control Register
* FPSR, Floating Poiht Status Register
*
* For A64 the FPSCR is split into two logically distinct registers,
* FPCR and FPSR. However since they still use non-overlapping bits * FPCR and FPSR. However since they still use non-overlapping bits
* we store the underlying state in fpscr and just mask on read/write. * we store the underlying state in fpscr and just mask on read/write.
*/ */
#define FPSR_MASK 0xf800009f #define FPSR_MASK 0xf800009f
#define FPCR_MASK 0x07f79f00 #define FPCR_MASK 0x07f79f00
#define FPCR_FZ16 (1 << 19) /* ARMv8.2+, FP16 flush-to-zero */
#define FPCR_FZ (1 << 24) /* Flush-to-zero enable bit */
#define FPCR_DN (1 << 25) /* Default NaN enable bit */
static inline uint32_t vfp_get_fpsr(CPUARMState *env) static inline uint32_t vfp_get_fpsr(CPUARMState *env)
{ {
return vfp_get_fpscr(env) & FPSR_MASK; return vfp_get_fpscr(env) & FPSR_MASK;

26
target/arm/helper.c
View File

@ -11103,6 +11103,7 @@ uint32_t HELPER(vfp_get_fpscr)(CPUARMState *env)
| (env->vfp.vec_stride << 20); | (env->vfp.vec_stride << 20);
i = get_float_exception_flags(&env->vfp.fp_status); i = get_float_exception_flags(&env->vfp.fp_status);
i |= get_float_exception_flags(&env->vfp.standard_fp_status); i |= get_float_exception_flags(&env->vfp.standard_fp_status);
i |= get_float_exception_flags(&env->vfp.fp_status_f16);
fpscr |= vfp_exceptbits_from_host(i); fpscr |= vfp_exceptbits_from_host(i);
return fpscr; return fpscr;
} }
@ -11160,16 +11161,31 @@ void HELPER(vfp_set_fpscr)(CPUARMState *env, uint32_t val)
break; break;
} }
set_float_rounding_mode(i, &env->vfp.fp_status); set_float_rounding_mode(i, &env->vfp.fp_status);
set_float_rounding_mode(i, &env->vfp.fp_status_f16);
} }
if (changed & (1 << 24)) { if (changed & FPCR_FZ16) {
set_flush_to_zero((val & (1 << 24)) != 0, &env->vfp.fp_status); bool ftz_enabled = val & FPCR_FZ16;
set_flush_inputs_to_zero((val & (1 << 24)) != 0, &env->vfp.fp_status); set_flush_to_zero(ftz_enabled, &env->vfp.fp_status_f16);
set_flush_inputs_to_zero(ftz_enabled, &env->vfp.fp_status_f16);
}
if (changed & FPCR_FZ) {
bool ftz_enabled = val & FPCR_FZ;
set_flush_to_zero(ftz_enabled, &env->vfp.fp_status);
set_flush_inputs_to_zero(ftz_enabled, &env->vfp.fp_status);
}
if (changed & FPCR_DN) {
bool dnan_enabled = val & FPCR_DN;
set_default_nan_mode(dnan_enabled, &env->vfp.fp_status);
set_default_nan_mode(dnan_enabled, &env->vfp.fp_status_f16);
} }
if (changed & (1 << 25))
set_default_nan_mode((val & (1 << 25)) != 0, &env->vfp.fp_status);
/* The exception flags are ORed together when we read fpscr so we
* only need to preserve the current state in one of our
* float_status values.
*/
i = vfp_exceptbits_to_host(val); i = vfp_exceptbits_to_host(val);
set_float_exception_flags(i, &env->vfp.fp_status); set_float_exception_flags(i, &env->vfp.fp_status);
set_float_exception_flags(0, &env->vfp.fp_status_f16);
set_float_exception_flags(0, &env->vfp.standard_fp_status); set_float_exception_flags(0, &env->vfp.standard_fp_status);
} }

51
target/arm/translate-a64.c
View File

@ -637,16 +637,21 @@ static void write_fp_sreg(DisasContext *s, int reg, TCGv_i32 v)
tcg_temp_free_i64(tmp); tcg_temp_free_i64(tmp);
} }
static TCGv_ptr get_fpstatus_ptr(void) static TCGv_ptr get_fpstatus_ptr(bool is_f16)
{ {
TCGv_ptr statusptr = tcg_temp_new_ptr(); TCGv_ptr statusptr = tcg_temp_new_ptr();
int offset; int offset;
/* In A64 all instructions (both FP and Neon) use the FPCR; /* In A64 all instructions (both FP and Neon) use the FPCR; there
* there is no equivalent of the A32 Neon "standard FPSCR value" * is no equivalent of the A32 Neon "standard FPSCR value".
* and all operations use vfp.fp_status. * However half-precision operations operate under a different
* FZ16 flag and use vfp.fp_status_f16 instead of vfp.fp_status.
*/ */
if (is_f16) {
offset = offsetof(CPUARMState, vfp.fp_status_f16);
} else {
offset = offsetof(CPUARMState, vfp.fp_status); offset = offsetof(CPUARMState, vfp.fp_status);
}
tcg_gen_addi_ptr(statusptr, cpu_env, offset); tcg_gen_addi_ptr(statusptr, cpu_env, offset);
return statusptr; return statusptr;
} }
@ -4423,7 +4428,7 @@ static void handle_fp_compare(DisasContext *s, bool is_double,
bool cmp_with_zero, bool signal_all_nans) bool cmp_with_zero, bool signal_all_nans)
{ {
TCGv_i64 tcg_flags = tcg_temp_new_i64(); TCGv_i64 tcg_flags = tcg_temp_new_i64();
TCGv_ptr fpst = get_fpstatus_ptr(); TCGv_ptr fpst = get_fpstatus_ptr(false);
if (is_double) { if (is_double) {
TCGv_i64 tcg_vn, tcg_vm; TCGv_i64 tcg_vn, tcg_vm;
@ -4598,7 +4603,7 @@ static void handle_fp_1src_single(DisasContext *s, int opcode, int rd, int rn)
TCGv_i32 tcg_op; TCGv_i32 tcg_op;
TCGv_i32 tcg_res; TCGv_i32 tcg_res;
fpst = get_fpstatus_ptr(); fpst = get_fpstatus_ptr(false);
tcg_op = read_fp_sreg(s, rn); tcg_op = read_fp_sreg(s, rn);
tcg_res = tcg_temp_new_i32(); tcg_res = tcg_temp_new_i32();
@ -4660,7 +4665,7 @@ static void handle_fp_1src_double(DisasContext *s, int opcode, int rd, int rn)
return; return;
} }
fpst = get_fpstatus_ptr(); fpst = get_fpstatus_ptr(false);
tcg_op = read_fp_dreg(s, rn); tcg_op = read_fp_dreg(s, rn);
tcg_res = tcg_temp_new_i64(); tcg_res = tcg_temp_new_i64();
@ -4840,7 +4845,7 @@ static void handle_fp_2src_single(DisasContext *s, int opcode,
TCGv_ptr fpst; TCGv_ptr fpst;
tcg_res = tcg_temp_new_i32(); tcg_res = tcg_temp_new_i32();
fpst = get_fpstatus_ptr(); fpst = get_fpstatus_ptr(false);
tcg_op1 = read_fp_sreg(s, rn); tcg_op1 = read_fp_sreg(s, rn);
tcg_op2 = read_fp_sreg(s, rm); tcg_op2 = read_fp_sreg(s, rm);
@ -4893,7 +4898,7 @@ static void handle_fp_2src_double(DisasContext *s, int opcode,
TCGv_ptr fpst; TCGv_ptr fpst;
tcg_res = tcg_temp_new_i64(); tcg_res = tcg_temp_new_i64();
fpst = get_fpstatus_ptr(); fpst = get_fpstatus_ptr(false);
tcg_op1 = read_fp_dreg(s, rn); tcg_op1 = read_fp_dreg(s, rn);
tcg_op2 = read_fp_dreg(s, rm); tcg_op2 = read_fp_dreg(s, rm);
@ -4979,7 +4984,7 @@ static void handle_fp_3src_single(DisasContext *s, bool o0, bool o1,
{ {
TCGv_i32 tcg_op1, tcg_op2, tcg_op3; TCGv_i32 tcg_op1, tcg_op2, tcg_op3;
TCGv_i32 tcg_res = tcg_temp_new_i32(); TCGv_i32 tcg_res = tcg_temp_new_i32();
TCGv_ptr fpst = get_fpstatus_ptr(); TCGv_ptr fpst = get_fpstatus_ptr(false);
tcg_op1 = read_fp_sreg(s, rn); tcg_op1 = read_fp_sreg(s, rn);
tcg_op2 = read_fp_sreg(s, rm); tcg_op2 = read_fp_sreg(s, rm);
@ -5017,7 +5022,7 @@ static void handle_fp_3src_double(DisasContext *s, bool o0, bool o1,
{ {
TCGv_i64 tcg_op1, tcg_op2, tcg_op3; TCGv_i64 tcg_op1, tcg_op2, tcg_op3;
TCGv_i64 tcg_res = tcg_temp_new_i64(); TCGv_i64 tcg_res = tcg_temp_new_i64();
TCGv_ptr fpst = get_fpstatus_ptr(); TCGv_ptr fpst = get_fpstatus_ptr(false);
tcg_op1 = read_fp_dreg(s, rn); tcg_op1 = read_fp_dreg(s, rn);
tcg_op2 = read_fp_dreg(s, rm); tcg_op2 = read_fp_dreg(s, rm);
@ -5158,7 +5163,7 @@ static void handle_fpfpcvt(DisasContext *s, int rd, int rn, int opcode,
TCGv_ptr tcg_fpstatus; TCGv_ptr tcg_fpstatus;
TCGv_i32 tcg_shift; TCGv_i32 tcg_shift;
tcg_fpstatus = get_fpstatus_ptr(); tcg_fpstatus = get_fpstatus_ptr(false);
tcg_shift = tcg_const_i32(64 - scale); tcg_shift = tcg_const_i32(64 - scale);
@ -5870,7 +5875,7 @@ static void disas_simd_across_lanes(DisasContext *s, uint32_t insn)
TCGv_i32 tcg_elt1 = tcg_temp_new_i32(); TCGv_i32 tcg_elt1 = tcg_temp_new_i32();
TCGv_i32 tcg_elt2 = tcg_temp_new_i32(); TCGv_i32 tcg_elt2 = tcg_temp_new_i32();
TCGv_i32 tcg_elt3 = tcg_temp_new_i32(); TCGv_i32 tcg_elt3 = tcg_temp_new_i32();
TCGv_ptr fpst = get_fpstatus_ptr(); TCGv_ptr fpst = get_fpstatus_ptr(false);
assert(esize == 32); assert(esize == 32);
assert(elements == 4); assert(elements == 4);
@ -6372,7 +6377,7 @@ static void disas_simd_scalar_pairwise(DisasContext *s, uint32_t insn)
} }
size = extract32(size, 0, 1) ? 3 : 2; size = extract32(size, 0, 1) ? 3 : 2;
fpst = get_fpstatus_ptr(); fpst = get_fpstatus_ptr(false);
break; break;
default: default:
unallocated_encoding(s); unallocated_encoding(s);
@ -6864,7 +6869,7 @@ static void handle_simd_intfp_conv(DisasContext *s, int rd, int rn,
int fracbits, int size) int fracbits, int size)
{ {
bool is_double = size == 3 ? true : false; bool is_double = size == 3 ? true : false;
TCGv_ptr tcg_fpst = get_fpstatus_ptr(); TCGv_ptr tcg_fpst = get_fpstatus_ptr(false);
TCGv_i32 tcg_shift = tcg_const_i32(fracbits); TCGv_i32 tcg_shift = tcg_const_i32(fracbits);
TCGv_i64 tcg_int = tcg_temp_new_i64(); TCGv_i64 tcg_int = tcg_temp_new_i64();
TCGMemOp mop = size | (is_signed ? MO_SIGN : 0); TCGMemOp mop = size | (is_signed ? MO_SIGN : 0);
@ -6980,7 +6985,7 @@ static void handle_simd_shift_fpint_conv(DisasContext *s, bool is_scalar,
tcg_rmode = tcg_const_i32(arm_rmode_to_sf(FPROUNDING_ZERO)); tcg_rmode = tcg_const_i32(arm_rmode_to_sf(FPROUNDING_ZERO));
gen_helper_set_rmode(tcg_rmode, tcg_rmode, cpu_env); gen_helper_set_rmode(tcg_rmode, tcg_rmode, cpu_env);
tcg_fpstatus = get_fpstatus_ptr(); tcg_fpstatus = get_fpstatus_ptr(false);
tcg_shift = tcg_const_i32(fracbits); tcg_shift = tcg_const_i32(fracbits);
if (is_double) { if (is_double) {
@ -7326,7 +7331,7 @@ static void handle_3same_float(DisasContext *s, int size, int elements,
int fpopcode, int rd, int rn, int rm) int fpopcode, int rd, int rn, int rm)
{ {
int pass; int pass;
TCGv_ptr fpst = get_fpstatus_ptr(); TCGv_ptr fpst = get_fpstatus_ptr(false);
for (pass = 0; pass < elements; pass++) { for (pass = 0; pass < elements; pass++) {
if (size) { if (size) {
@ -7790,7 +7795,7 @@ static void handle_2misc_fcmp_zero(DisasContext *s, int opcode,
return; return;
} }
fpst = get_fpstatus_ptr(); fpst = get_fpstatus_ptr(false);
if (is_double) { if (is_double) {
TCGv_i64 tcg_op = tcg_temp_new_i64(); TCGv_i64 tcg_op = tcg_temp_new_i64();
@ -7897,7 +7902,7 @@ static void handle_2misc_reciprocal(DisasContext *s, int opcode,
int size, int rn, int rd) int size, int rn, int rd)
{ {
bool is_double = (size == 3); bool is_double = (size == 3);
TCGv_ptr fpst = get_fpstatus_ptr(); TCGv_ptr fpst = get_fpstatus_ptr(false);
if (is_double) { if (is_double) {
TCGv_i64 tcg_op = tcg_temp_new_i64(); TCGv_i64 tcg_op = tcg_temp_new_i64();
@ -8296,7 +8301,7 @@ static void disas_simd_scalar_two_reg_misc(DisasContext *s, uint32_t insn)
if (is_fcvt) { if (is_fcvt) {
tcg_rmode = tcg_const_i32(arm_rmode_to_sf(rmode)); tcg_rmode = tcg_const_i32(arm_rmode_to_sf(rmode));
gen_helper_set_rmode(tcg_rmode, tcg_rmode, cpu_env); gen_helper_set_rmode(tcg_rmode, tcg_rmode, cpu_env);
tcg_fpstatus = get_fpstatus_ptr(); tcg_fpstatus = get_fpstatus_ptr(false);
} else { } else {
tcg_rmode = NULL; tcg_rmode = NULL;
tcg_fpstatus = NULL; tcg_fpstatus = NULL;
@ -9516,7 +9521,7 @@ static void handle_simd_3same_pair(DisasContext *s, int is_q, int u, int opcode,
/* Floating point operations need fpst */ /* Floating point operations need fpst */
if (opcode >= 0x58) { if (opcode >= 0x58) {
fpst = get_fpstatus_ptr(); fpst = get_fpstatus_ptr(false);
} else { } else {
fpst = NULL; fpst = NULL;
} }
@ -10676,7 +10681,7 @@ static void disas_simd_two_reg_misc(DisasContext *s, uint32_t insn)
} }
if (need_fpstatus) { if (need_fpstatus) {
tcg_fpstatus = get_fpstatus_ptr(); tcg_fpstatus = get_fpstatus_ptr(false);
} else { } else {
tcg_fpstatus = NULL; tcg_fpstatus = NULL;
} }
@ -11056,7 +11061,7 @@ static void disas_simd_indexed(DisasContext *s, uint32_t insn)
} }
if (is_fp) { if (is_fp) {
fpst = get_fpstatus_ptr(); fpst = get_fpstatus_ptr(false);
} else { } else {
fpst = NULL; fpst = NULL;
} }