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target-s390: Convert ADD HALFWORD

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Signed-off-by: Richard Henderson <rth@twiddle.net>
This commit is contained in:
Richard Henderson 2012-08-16 14:09:45 -07:00
parent d5a103cd6e
commit d82287dee9
2 changed files with 14 additions and 36 deletions
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7
target-s390x/insn-data.def
View File

@ -15,6 +15,13 @@
C(0xc208, AGFI, RIL_a, EI, r1, i2, r1, 0, add, adds64)
C(0xeb7a, AGSI, SIY, GIE, m1_64, i2, new, m1_64, add, adds64)
C(0xecd9, AGHIK, RIE_d, DO, r3, i2, r1, 0, add, adds64)
/* ADD HALFWORD */
C(0x4a00, AH, RX_a, Z, r1, m2_16s, new, r1_32, add, adds32)
C(0xe37a, AHY, RXY_a, LD, r1, m2_16s, new, r1_32, add, adds32)
/* ADD HALFWORD IMMEDIATE */
C(0xa70a, AHI, RI_a, Z, r1, i2, new, r1_32, add, adds32)
C(0xa70b, AGHI, RI_a, Z, r1, i2, r1, 0, add, adds64)
/* ADD LOGICAL */
C(0x1e00, ALR, RR_a, Z, r1, r2, new, r1_32, add, addu32)
C(0xb9fa, ALRK, RRF_a, DO, r2, r3, new, r1_32, add, addu32)

43
target-s390x/translate.c
View File

@ -559,11 +559,6 @@ static inline void set_cc_s64(DisasContext *s, TCGv_i64 val)
gen_op_update1_cc_i64(s, CC_OP_LTGT0_64, val);
}
static void set_cc_add64(DisasContext *s, TCGv_i64 v1, TCGv_i64 v2, TCGv_i64 vr)
{
gen_op_update3_cc_i64(s, CC_OP_ADD_64, v1, v2, vr);
}
static void set_cc_addu64(DisasContext *s, TCGv_i64 v1, TCGv_i64 v2,
TCGv_i64 vr)
{
@ -2267,7 +2262,7 @@ static void disas_a7(CPUS390XState *env, DisasContext *s, int op, int r1,
int i2)
{
TCGv_i64 tmp, tmp2;
TCGv_i32 tmp32_1, tmp32_2, tmp32_3;
TCGv_i32 tmp32_1;
int l1;
LOG_DISAS("disas_a7: op 0x%x r1 %d i2 0x%x\n", op, r1, i2);
@ -2342,36 +2337,6 @@ static void disas_a7(CPUS390XState *env, DisasContext *s, int op, int r1,
store_reg(r1, tmp);
tcg_temp_free_i64(tmp);
break;
case 0xa: /* AHI R1,I2 [RI] */
tmp32_1 = load_reg32(r1);
tmp32_2 = tcg_temp_new_i32();
tmp32_3 = tcg_const_i32(i2);
if (i2 < 0) {
tcg_gen_subi_i32(tmp32_2, tmp32_1, -i2);
} else {
tcg_gen_add_i32(tmp32_2, tmp32_1, tmp32_3);
}
store_reg32(r1, tmp32_2);
set_cc_add32(s, tmp32_1, tmp32_3, tmp32_2);
tcg_temp_free_i32(tmp32_1);
tcg_temp_free_i32(tmp32_2);
tcg_temp_free_i32(tmp32_3);
break;
case 0xb: /* aghi r1, i2 */
tmp = load_reg(r1);
tmp2 = tcg_const_i64(i2);
if (i2 < 0) {
tcg_gen_subi_i64(regs[r1], tmp, -i2);
} else {
tcg_gen_add_i64(regs[r1], tmp, tmp2);
}
set_cc_add64(s, tmp, tmp2, regs[r1]);
tcg_temp_free_i64(tmp);
tcg_temp_free_i64(tmp2);
break;
case 0xc: /* MHI R1,I2 [RI] */
tmp32_1 = load_reg32(r1);
tcg_gen_muli_i32(tmp32_1, tmp32_1, i2);
@ -5078,6 +5043,12 @@ static void in2_a2(DisasContext *s, DisasFields *f, DisasOps *o)
o->in2 = get_address(s, x2, get_field(f, b2), get_field(f, d2));
}
static void in2_m2_16s(DisasContext *s, DisasFields *f, DisasOps *o)
{
in2_a2(s, f, o);
tcg_gen_qemu_ld16s(o->in2, o->in2, get_mem_index(s));
}
static void in2_m2_32s(DisasContext *s, DisasFields *f, DisasOps *o)
{
in2_a2(s, f, o);