PPC: rename cpu_ppc_reset to cpu_reset for consistency
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
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44a9935465
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d84bda46de
@ -416,7 +416,7 @@ int cpu_exec(CPUState *env1)
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#elif defined(TARGET_PPC)
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#if 0
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if ((interrupt_request & CPU_INTERRUPT_RESET)) {
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cpu_ppc_reset(env);
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cpu_reset(env);
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}
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#endif
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if (interrupt_request & CPU_INTERRUPT_HARD) {
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4
hw/ppc.c
4
hw/ppc.c
@ -123,7 +123,7 @@ static void ppc6xx_set_irq (void *opaque, int pin, int level)
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env->interrupt_request |= CPU_INTERRUPT_EXITTB;
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/* XXX: TOFIX */
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#if 0
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cpu_ppc_reset(env);
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cpu_reset(env);
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#else
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qemu_system_reset_request();
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#endif
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@ -1088,7 +1088,7 @@ int ppc_dcr_init (CPUState *env, int (*read_error)(int dcrn),
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#if 0
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/*****************************************************************************/
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/* Handle system reset (for now, just stop emulation) */
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void cpu_ppc_reset (CPUState *env)
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void cpu_reset(CPUState *env)
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{
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printf("Reset asked... Stop emulation\n");
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abort();
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@ -1805,7 +1805,7 @@ void ppc40x_core_reset (CPUState *env)
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env->interrupt_request |= CPU_INTERRUPT_EXITTB;
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/* XXX: TOFIX */
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#if 0
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cpu_ppc_reset(env);
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cpu_reset(env);
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#else
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qemu_system_reset_request();
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#endif
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@ -1823,7 +1823,7 @@ void ppc40x_chip_reset (CPUState *env)
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env->interrupt_request |= CPU_INTERRUPT_EXITTB;
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/* XXX: TOFIX */
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#if 0
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cpu_ppc_reset(env);
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cpu_reset(env);
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#else
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qemu_system_reset_request();
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#endif
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@ -60,7 +60,7 @@ CPUState *ppc4xx_init (const char *cpu_model,
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tb_clk->opaque = env;
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ppc_dcr_init(env, NULL, NULL);
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/* Register qemu callbacks */
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qemu_register_reset(&cpu_ppc_reset, env);
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qemu_register_reset((QEMUResetHandler*)&cpu_reset, env);
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return env;
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}
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@ -130,7 +130,7 @@ static void ppc_core99_init (ram_addr_t ram_size,
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#if 0
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env->osi_call = vga_osi_call;
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#endif
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qemu_register_reset(&cpu_ppc_reset, env);
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qemu_register_reset((QEMUResetHandler*)&cpu_reset, env);
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envs[i] = env;
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}
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@ -158,7 +158,7 @@ static void ppc_heathrow_init (ram_addr_t ram_size,
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/* Set time-base frequency to 16.6 Mhz */
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cpu_ppc_tb_init(env, 16600000UL);
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env->osi_call = vga_osi_call;
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qemu_register_reset(&cpu_ppc_reset, env);
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qemu_register_reset((QEMUResetHandler*)&cpu_reset, env);
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envs[i] = env;
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}
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@ -586,7 +586,7 @@ static void ppc_prep_init (ram_addr_t ram_size,
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/* Set time-base frequency to 100 Mhz */
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cpu_ppc_tb_init(env, 100UL * 1000UL * 1000UL);
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}
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qemu_register_reset(&cpu_ppc_reset, env);
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qemu_register_reset((QEMUResetHandler*)&cpu_reset, env);
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envs[i] = env;
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}
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@ -734,8 +734,6 @@ void ppc_store_sr (CPUPPCState *env, int srnum, target_ulong value);
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#endif /* !defined(CONFIG_USER_ONLY) */
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void ppc_store_msr (CPUPPCState *env, target_ulong value);
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void cpu_ppc_reset (void *opaque);
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void ppc_cpu_list (FILE *f, int (*cpu_fprintf)(FILE *f, const char *fmt, ...));
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const ppc_def_t *cpu_ppc_find_by_name (const char *name);
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@ -2748,9 +2748,8 @@ void cpu_dump_rfi (target_ulong RA, target_ulong msr)
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TARGET_FMT_lx "\n", RA, msr);
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}
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void cpu_ppc_reset (void *opaque)
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void cpu_reset(CPUPPCState *env)
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{
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CPUPPCState *env = opaque;
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target_ulong msr;
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if (qemu_loglevel_mask(CPU_LOG_RESET)) {
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@ -2812,7 +2811,7 @@ CPUPPCState *cpu_ppc_init (const char *cpu_model)
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env->cpu_model_str = cpu_model;
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cpu_ppc_register_internal(env, def);
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#if defined(CONFIG_USER_ONLY)
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cpu_ppc_reset(env);
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cpu_reset(env);
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#endif
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qemu_init_vcpu(env);
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