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igb: Add Function Level Reset to PF and VF

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The Intel 82576EB GbE Controller say that the Physical and Virtual
Functions support Function Level Reset. Add the capability to the PF
device model using device property "x-pcie-flr-init" which is "on" by
default and "off" for machines <= 8.1 to preserve compatibility.

The FLR capability of the VF model is defined according to the FLR
property of the PF, this to avoid adding an extra compatibility
property.

Cc: Sriram Yagnaraman <sriram.yagnaraman@est.tech>
Fixes: 3a977deebe ("Intrdocue igb device emulation")
Reviewed-by: Akihiko Odaki <akihiko.odaki@daynix.com>
Tested-by: Akihiko Odaki <akihiko.odaki@daynix.com>
Signed-off-by: Cédric Le Goater <clg@redhat.com>
Signed-off-by: Jason Wang <jasowang@redhat.com>
This commit is contained in:
Cédric Le Goater 2023-10-23 17:45:07 +02:00 committed by Jason Wang
parent fe73674af1
commit d90014fc33
3 changed files with 20 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

3
hw/core/machine.c
View File

@ -35,7 +35,8 @@
GlobalProperty hw_compat_8_1[] = {
{ TYPE_PCI_BRIDGE, "x-pci-express-writeable-slt-bug", "true" },
{ "ramfb", "x-migrate", "off" },
{ "vfio-pci-nohotplug", "x-ramfb-migrate", "off" }
{ "vfio-pci-nohotplug", "x-ramfb-migrate", "off" },
{ "igb", "x-pcie-flr-init", "off" },
};
const size_t hw_compat_8_1_len = G_N_ELEMENTS(hw_compat_8_1);

9
hw/net/igb.c
View File

@ -78,6 +78,7 @@ struct IGBState {
uint32_t ioaddr;
IGBCore core;
bool has_flr;
};
#define IGB_CAP_SRIOV_OFFSET (0x160)
@ -101,6 +102,9 @@ static void igb_write_config(PCIDevice *dev, uint32_t addr,
trace_igb_write_config(addr, val, len);
pci_default_write_config(dev, addr, val, len);
if (s->has_flr) {
pcie_cap_flr_write_config(dev, addr, val, len);
}
if (range_covers_byte(addr, len, PCI_COMMAND) &&
(dev->config[PCI_COMMAND] & PCI_COMMAND_MASTER)) {
@ -433,6 +437,10 @@ static void igb_pci_realize(PCIDevice *pci_dev, Error **errp)
}
/* PCIe extended capabilities (in order) */
if (s->has_flr) {
pcie_cap_flr_init(pci_dev);
}
if (pcie_aer_init(pci_dev, 1, 0x100, 0x40, errp) < 0) {
hw_error("Failed to initialize AER capability");
}
@ -588,6 +596,7 @@ static const VMStateDescription igb_vmstate = {
static Property igb_properties[] = {
DEFINE_NIC_PROPERTIES(IGBState, conf),
DEFINE_PROP_BOOL("x-pcie-flr-init", IGBState, has_flr, true),
DEFINE_PROP_END_OF_LIST(),
};

9
hw/net/igbvf.c
View File

@ -204,6 +204,10 @@ static void igbvf_write_config(PCIDevice *dev, uint32_t addr, uint32_t val,
{
trace_igbvf_write_config(addr, val, len);
pci_default_write_config(dev, addr, val, len);
if (object_property_get_bool(OBJECT(pcie_sriov_get_pf(dev)),
"x-pcie-flr-init", &error_abort)) {
pcie_cap_flr_write_config(dev, addr, val, len);
}
}
static uint64_t igbvf_mmio_read(void *opaque, hwaddr addr, unsigned size)
@ -266,6 +270,11 @@ static void igbvf_pci_realize(PCIDevice *dev, Error **errp)
hw_error("Failed to initialize PCIe capability");
}
if (object_property_get_bool(OBJECT(pcie_sriov_get_pf(dev)),
"x-pcie-flr-init", &error_abort)) {
pcie_cap_flr_init(dev);
}
if (pcie_aer_init(dev, 1, 0x100, 0x40, errp) < 0) {
hw_error("Failed to initialize AER capability");
}