From d909808ec002abee64209a967d636878afe280b5 Mon Sep 17 00:00:00 2001 From: Paolo Montesel Date: Fri, 23 Sep 2022 19:38:23 +0200 Subject: [PATCH] target/hexagon: make slot number an unsigned Signed-off-by: Alessandro Di Federico Signed-off-by: Paolo Montesel Signed-off-by: Taylor Simpson Acked-by: Richard Henderson Reviewed-by: Taylor Simpson Message-Id: <20220923173831.227551-4-anjo@rev.ng> --- target/hexagon/genptr.c | 24 +++++++++++++----------- target/hexagon/macros.h | 2 +- 2 files changed, 14 insertions(+), 12 deletions(-) diff --git a/target/hexagon/genptr.c b/target/hexagon/genptr.c index a4a79c8454..4cd2a2aeb9 100644 --- a/target/hexagon/genptr.c +++ b/target/hexagon/genptr.c @@ -30,7 +30,8 @@ #include "gen_tcg.h" #include "gen_tcg_hvx.h" -static inline void gen_log_predicated_reg_write(int rnum, TCGv val, int slot) +static inline void gen_log_predicated_reg_write(int rnum, TCGv val, + uint32_t slot) { TCGv zero = tcg_constant_tl(0); TCGv slot_mask = tcg_temp_new(); @@ -62,7 +63,8 @@ static inline void gen_log_reg_write(int rnum, TCGv val) } } -static void gen_log_predicated_reg_write_pair(int rnum, TCGv_i64 val, int slot) +static void gen_log_predicated_reg_write_pair(int rnum, TCGv_i64 val, + uint32_t slot) { TCGv val32 = tcg_temp_new(); TCGv zero = tcg_constant_tl(0); @@ -394,54 +396,54 @@ static inline void gen_store_conditional8(DisasContext *ctx, tcg_gen_movi_tl(hex_llsc_addr, ~0); } -static inline void gen_store32(TCGv vaddr, TCGv src, int width, int slot) +static inline void gen_store32(TCGv vaddr, TCGv src, int width, uint32_t slot) { tcg_gen_mov_tl(hex_store_addr[slot], vaddr); tcg_gen_movi_tl(hex_store_width[slot], width); tcg_gen_mov_tl(hex_store_val32[slot], src); } -static inline void gen_store1(TCGv_env cpu_env, TCGv vaddr, TCGv src, int slot) +static inline void gen_store1(TCGv_env cpu_env, TCGv vaddr, TCGv src, uint32_t slot) { gen_store32(vaddr, src, 1, slot); } -static inline void gen_store1i(TCGv_env cpu_env, TCGv vaddr, int32_t src, int slot) +static inline void gen_store1i(TCGv_env cpu_env, TCGv vaddr, int32_t src, uint32_t slot) { TCGv tmp = tcg_constant_tl(src); gen_store1(cpu_env, vaddr, tmp, slot); } -static inline void gen_store2(TCGv_env cpu_env, TCGv vaddr, TCGv src, int slot) +static inline void gen_store2(TCGv_env cpu_env, TCGv vaddr, TCGv src, uint32_t slot) { gen_store32(vaddr, src, 2, slot); } -static inline void gen_store2i(TCGv_env cpu_env, TCGv vaddr, int32_t src, int slot) +static inline void gen_store2i(TCGv_env cpu_env, TCGv vaddr, int32_t src, uint32_t slot) { TCGv tmp = tcg_constant_tl(src); gen_store2(cpu_env, vaddr, tmp, slot); } -static inline void gen_store4(TCGv_env cpu_env, TCGv vaddr, TCGv src, int slot) +static inline void gen_store4(TCGv_env cpu_env, TCGv vaddr, TCGv src, uint32_t slot) { gen_store32(vaddr, src, 4, slot); } -static inline void gen_store4i(TCGv_env cpu_env, TCGv vaddr, int32_t src, int slot) +static inline void gen_store4i(TCGv_env cpu_env, TCGv vaddr, int32_t src, uint32_t slot) { TCGv tmp = tcg_constant_tl(src); gen_store4(cpu_env, vaddr, tmp, slot); } -static inline void gen_store8(TCGv_env cpu_env, TCGv vaddr, TCGv_i64 src, int slot) +static inline void gen_store8(TCGv_env cpu_env, TCGv vaddr, TCGv_i64 src, uint32_t slot) { tcg_gen_mov_tl(hex_store_addr[slot], vaddr); tcg_gen_movi_tl(hex_store_width[slot], 8); tcg_gen_mov_i64(hex_store_val64[slot], src); } -static inline void gen_store8i(TCGv_env cpu_env, TCGv vaddr, int64_t src, int slot) +static inline void gen_store8i(TCGv_env cpu_env, TCGv vaddr, int64_t src, uint32_t slot) { TCGv_i64 tmp = tcg_constant_i64(src); gen_store8(cpu_env, vaddr, tmp, slot); diff --git a/target/hexagon/macros.h b/target/hexagon/macros.h index 903503540e..1a31542010 100644 --- a/target/hexagon/macros.h +++ b/target/hexagon/macros.h @@ -202,7 +202,7 @@ #define LOAD_CANCEL(EA) do { CANCEL; } while (0) #ifdef QEMU_GENERATE -static inline void gen_pred_cancel(TCGv pred, int slot_num) +static inline void gen_pred_cancel(TCGv pred, uint32_t slot_num) { TCGv slot_mask = tcg_temp_new(); TCGv tmp = tcg_temp_new();