target/ppc: Introduce ppc_radix64_xlate() for Radix tree translation
This is moving code under a new ppc_radix64_xlate() routine shared by the MMU Radix page fault handler and the 'get_phys_page_debug' PPC callback. The difference being that 'get_phys_page_debug' does not generate exceptions. The specific part of process-scoped Radix translation is moved under ppc_radix64_process_scoped_xlate() in preparation of the future support for partition-scoped Radix translation. Routines raising the exceptions now take a 'cause_excp' bool to cover the 'get_phys_page_debug' case. It should be functionally equivalent. Signed-off-by: Suraj Jitindar Singh <sjitindarsingh@gmail.com> Signed-off-by: Cédric Le Goater <clg@kaod.org> Message-Id: <20200403140056.59465-2-clg@kaod.org> Reviewed-by: Greg Kurz <groug@kaod.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
This commit is contained in:
Cédric Le Goater
David Gibson
parent
05af7c77f5
commit
d92baf00aa
@ -219,17 +219,127 @@ static bool validate_pate(PowerPCCPU *cpu, uint64_t lpid, ppc_v3_pate_t *pate)
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return true;
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}
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static int ppc_radix64_process_scoped_xlate(PowerPCCPU *cpu, int rwx,
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vaddr eaddr, uint64_t pid,
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ppc_v3_pate_t pate, hwaddr *g_raddr,
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int *g_prot, int *g_page_size,
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bool cause_excp)
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{
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CPUState *cs = CPU(cpu);
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uint64_t offset, size, prtbe_addr, prtbe0, pte;
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int fault_cause = 0;
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hwaddr pte_addr;
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/* Index Process Table by PID to Find Corresponding Process Table Entry */
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offset = pid * sizeof(struct prtb_entry);
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size = 1ULL << ((pate.dw1 & PATE1_R_PRTS) + 12);
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if (offset >= size) {
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/* offset exceeds size of the process table */
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if (cause_excp) {
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ppc_radix64_raise_si(cpu, rwx, eaddr, DSISR_NOPTE);
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}
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return 1;
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}
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prtbe_addr = (pate.dw1 & PATE1_R_PRTB) + offset;
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prtbe0 = ldq_phys(cs->as, prtbe_addr);
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/* Walk Radix Tree from Process Table Entry to Convert EA to RA */
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*g_page_size = PRTBE_R_GET_RTS(prtbe0);
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pte = ppc_radix64_walk_tree(cpu, eaddr & R_EADDR_MASK,
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prtbe0 & PRTBE_R_RPDB, prtbe0 & PRTBE_R_RPDS,
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g_raddr, g_page_size, &fault_cause, &pte_addr);
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if (!(pte & R_PTE_VALID) ||
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ppc_radix64_check_prot(cpu, rwx, pte, &fault_cause, g_prot)) {
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/* No valid pte or access denied due to protection */
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if (cause_excp) {
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ppc_radix64_raise_si(cpu, rwx, eaddr, fault_cause);
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}
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return 1;
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}
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ppc_radix64_set_rc(cpu, rwx, pte, pte_addr, g_prot);
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return 0;
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}
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static int ppc_radix64_xlate(PowerPCCPU *cpu, vaddr eaddr, int rwx,
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bool relocation,
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hwaddr *raddr, int *psizep, int *protp,
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bool cause_excp)
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{
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uint64_t lpid = 0, pid = 0;
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ppc_v3_pate_t pate;
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int psize, prot;
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hwaddr g_raddr;
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/* Virtual Mode Access - get the fully qualified address */
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if (!ppc_radix64_get_fully_qualified_addr(&cpu->env, eaddr, &lpid, &pid)) {
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if (cause_excp) {
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ppc_radix64_raise_segi(cpu, rwx, eaddr);
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}
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return 1;
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}
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/* Get Process Table */
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if (cpu->vhyp) {
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PPCVirtualHypervisorClass *vhc;
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vhc = PPC_VIRTUAL_HYPERVISOR_GET_CLASS(cpu->vhyp);
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vhc->get_pate(cpu->vhyp, &pate);
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} else {
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if (!ppc64_v3_get_pate(cpu, lpid, &pate)) {
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if (cause_excp) {
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ppc_radix64_raise_si(cpu, rwx, eaddr, DSISR_NOPTE);
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}
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return 1;
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}
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if (!validate_pate(cpu, lpid, &pate)) {
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if (cause_excp) {
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ppc_radix64_raise_si(cpu, rwx, eaddr, DSISR_R_BADCONFIG);
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}
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return 1;
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}
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/* We don't support guest mode yet */
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if (lpid != 0) {
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error_report("PowerNV guest support Unimplemented");
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exit(1);
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}
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}
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*psizep = INT_MAX;
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*protp = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
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/*
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* Perform process-scoped translation if relocation enabled.
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*
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* - Translates an effective address to a host real address in
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* quadrants 0 and 3 when HV=1.
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*/
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if (relocation) {
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int ret = ppc_radix64_process_scoped_xlate(cpu, rwx, eaddr, pid,
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pate, &g_raddr, &prot,
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&psize, cause_excp);
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if (ret) {
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return ret;
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}
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*psizep = MIN(*psizep, psize);
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*protp &= prot;
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} else {
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g_raddr = eaddr & R_EADDR_MASK;
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}
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*raddr = g_raddr;
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return 0;
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}
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int ppc_radix64_handle_mmu_fault(PowerPCCPU *cpu, vaddr eaddr, int rwx,
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int mmu_idx)
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{
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CPUState *cs = CPU(cpu);
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CPUPPCState *env = &cpu->env;
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PPCVirtualHypervisorClass *vhc;
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hwaddr raddr, pte_addr;
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uint64_t lpid = 0, pid = 0, offset, size, prtbe0, pte;
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int page_size, prot, fault_cause = 0;
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ppc_v3_pate_t pate;
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int page_size, prot;
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bool relocation;
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hwaddr raddr;
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assert(!(msr_hv && cpu->vhyp));
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assert((rwx == 0) || (rwx == 1) || (rwx == 2));
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@ -262,55 +372,12 @@ int ppc_radix64_handle_mmu_fault(PowerPCCPU *cpu, vaddr eaddr, int rwx,
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TARGET_FMT_lx "\n", env->spr[SPR_LPCR]);
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}
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/* Virtual Mode Access - get the fully qualified address */
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if (!ppc_radix64_get_fully_qualified_addr(env, eaddr, &lpid, &pid)) {
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ppc_radix64_raise_segi(cpu, rwx, eaddr);
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/* Translate eaddr to raddr (where raddr is addr qemu needs for access) */
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if (ppc_radix64_xlate(cpu, eaddr, rwx, relocation, &raddr,
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&page_size, &prot, true)) {
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return 1;
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}
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/* Get Process Table */
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if (cpu->vhyp) {
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vhc = PPC_VIRTUAL_HYPERVISOR_GET_CLASS(cpu->vhyp);
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vhc->get_pate(cpu->vhyp, &pate);
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} else {
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if (!ppc64_v3_get_pate(cpu, lpid, &pate)) {
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ppc_radix64_raise_si(cpu, rwx, eaddr, DSISR_NOPTE);
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return 1;
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}
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if (!validate_pate(cpu, lpid, &pate)) {
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ppc_radix64_raise_si(cpu, rwx, eaddr, DSISR_R_BADCONFIG);
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}
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/* We don't support guest mode yet */
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if (lpid != 0) {
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error_report("PowerNV guest support Unimplemented");
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exit(1);
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}
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}
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/* Index Process Table by PID to Find Corresponding Process Table Entry */
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offset = pid * sizeof(struct prtb_entry);
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size = 1ULL << ((pate.dw1 & PATE1_R_PRTS) + 12);
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if (offset >= size) {
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/* offset exceeds size of the process table */
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ppc_radix64_raise_si(cpu, rwx, eaddr, DSISR_NOPTE);
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return 1;
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}
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prtbe0 = ldq_phys(cs->as, (pate.dw1 & PATE1_R_PRTB) + offset);
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/* Walk Radix Tree from Process Table Entry to Convert EA to RA */
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page_size = PRTBE_R_GET_RTS(prtbe0);
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pte = ppc_radix64_walk_tree(cpu, eaddr & R_EADDR_MASK,
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prtbe0 & PRTBE_R_RPDB, prtbe0 & PRTBE_R_RPDS,
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&raddr, &page_size, &fault_cause, &pte_addr);
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if (!pte || ppc_radix64_check_prot(cpu, rwx, pte, &fault_cause, &prot)) {
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/* Couldn't get pte or access denied due to protection */
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ppc_radix64_raise_si(cpu, rwx, eaddr, fault_cause);
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return 1;
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}
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/* Update Reference and Change Bits */
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ppc_radix64_set_rc(cpu, rwx, pte, pte_addr, &prot);
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tlb_set_page(cs, eaddr & TARGET_PAGE_MASK, raddr & TARGET_PAGE_MASK,
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prot, mmu_idx, 1UL << page_size);
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return 0;
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@ -318,58 +385,18 @@ int ppc_radix64_handle_mmu_fault(PowerPCCPU *cpu, vaddr eaddr, int rwx,
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hwaddr ppc_radix64_get_phys_page_debug(PowerPCCPU *cpu, target_ulong eaddr)
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{
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CPUState *cs = CPU(cpu);
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CPUPPCState *env = &cpu->env;
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PPCVirtualHypervisorClass *vhc;
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hwaddr raddr, pte_addr;
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uint64_t lpid = 0, pid = 0, offset, size, prtbe0, pte;
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int page_size, fault_cause = 0;
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ppc_v3_pate_t pate;
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int psize, prot;
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hwaddr raddr;
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/* Handle Real Mode */
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if (msr_dr == 0) {
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if ((msr_dr == 0) && (msr_hv || cpu->vhyp)) {
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/* In real mode top 4 effective addr bits (mostly) ignored */
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return eaddr & 0x0FFFFFFFFFFFFFFFULL;
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}
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/* Virtual Mode Access - get the fully qualified address */
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if (!ppc_radix64_get_fully_qualified_addr(env, eaddr, &lpid, &pid)) {
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return -1;
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}
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/* Get Process Table */
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if (cpu->vhyp) {
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vhc = PPC_VIRTUAL_HYPERVISOR_GET_CLASS(cpu->vhyp);
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vhc->get_pate(cpu->vhyp, &pate);
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} else {
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if (!ppc64_v3_get_pate(cpu, lpid, &pate)) {
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return -1;
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}
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if (!validate_pate(cpu, lpid, &pate)) {
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return -1;
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}
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/* We don't support guest mode yet */
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if (lpid != 0) {
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error_report("PowerNV guest support Unimplemented");
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exit(1);
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}
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}
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/* Index Process Table by PID to Find Corresponding Process Table Entry */
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offset = pid * sizeof(struct prtb_entry);
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size = 1ULL << ((pate.dw1 & PATE1_R_PRTS) + 12);
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if (offset >= size) {
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/* offset exceeds size of the process table */
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return -1;
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}
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prtbe0 = ldq_phys(cs->as, (pate.dw1 & PATE1_R_PRTB) + offset);
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/* Walk Radix Tree from Process Table Entry to Convert EA to RA */
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page_size = PRTBE_R_GET_RTS(prtbe0);
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pte = ppc_radix64_walk_tree(cpu, eaddr & R_EADDR_MASK,
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prtbe0 & PRTBE_R_RPDB, prtbe0 & PRTBE_R_RPDS,
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&raddr, &page_size, &fault_cause, &pte_addr);
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if (!pte) {
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if (ppc_radix64_xlate(cpu, eaddr, 0, msr_dr, &raddr, &psize,
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&prot, false)) {
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return -1;
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}
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