From 5b4a047fbe8ceb68ad1a78d51f0fadbe2bb12af7 Mon Sep 17 00:00:00 2001 From: Alistair Francis Date: Tue, 24 Nov 2015 14:12:15 +0000 Subject: [PATCH 1/4] xlnx-ep108: Fix minimum RAM check The minimum RAM check logic for the Xiilnx EP108 was off by one, which caused a false positive. Correct the logic to only print warnings when the RAM is below 0x8000000. Signed-off-by: Alistair Francis Message-id: fba8112ca7b01efd72553332b8045ecf107b7662.1448021100.git.alistair.francis@xilinx.com Signed-off-by: Peter Maydell --- hw/arm/xlnx-ep108.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/hw/arm/xlnx-ep108.c b/hw/arm/xlnx-ep108.c index 2899698443..85b978fa76 100644 --- a/hw/arm/xlnx-ep108.c +++ b/hw/arm/xlnx-ep108.c @@ -51,7 +51,7 @@ static void xlnx_ep108_init(MachineState *machine) machine->ram_size = EP108_MAX_RAM_SIZE; } - if (machine->ram_size <= 0x08000000) { + if (machine->ram_size < 0x08000000) { qemu_log("WARNING: RAM size " RAM_ADDR_FMT " is small for EP108", machine->ram_size); } From f72c0a79f76f1b7ed1a1e0ff8be31f5df06b3269 Mon Sep 17 00:00:00 2001 From: Peter Maydell Date: Tue, 24 Nov 2015 14:12:15 +0000 Subject: [PATCH 2/4] default-configs/aarch64-linux-user.mak: Remove unused define The uses of the CONFIG_GDBSTUB_XML define were removed in commit b77abd95a9484c, but the define in aarch64-linux-user.mak somehow escaped the cull (the patchset probably crossed in the mail with the patches adding aarch64 support). Remove the stray define. Signed-off-by: Peter Maydell Reviewed-by: Laurent Desnogues Message-id: 1447690178-4560-1-git-send-email-peter.maydell@linaro.org --- default-configs/aarch64-linux-user.mak | 2 -- 1 file changed, 2 deletions(-) diff --git a/default-configs/aarch64-linux-user.mak b/default-configs/aarch64-linux-user.mak index 3df7de5b8f..0a5b08a007 100644 --- a/default-configs/aarch64-linux-user.mak +++ b/default-configs/aarch64-linux-user.mak @@ -1,3 +1 @@ # Default configuration for aarch64-linux-user - -CONFIG_GDBSTUB_XML=y From 6109769a8b42bd0c3d5b1601c9b35fe7ea6a603e Mon Sep 17 00:00:00 2001 From: Peter Maydell Date: Tue, 24 Nov 2015 14:12:15 +0000 Subject: [PATCH 3/4] target-arm: Don't mask out bits [47:40] in LPAE descriptors for v8 In an LPAE format descriptor in ARMv8 the address field extends up to bit 47, not just bit 39. Correct the masking so we don't give incorrect results if the output address size is greater than 40 bits, as it can be for AArch64. (Note that we don't yet support the new-in-v8 Address Size fault which should be generated if any translation table entry or TTBR contains an address with non-zero bits above the most significant bit of the maximum output address size.) Signed-off-by: Peter Maydell Reviewed-by: Laurent Desnogues Reviewed-by: Edgar E. Iglesias Message-id: 1448029971-9875-1-git-send-email-peter.maydell@linaro.org --- target-arm/helper.c | 12 +++++++++++- 1 file changed, 11 insertions(+), 1 deletion(-) diff --git a/target-arm/helper.c b/target-arm/helper.c index 4ecae61197..afc4163342 100644 --- a/target-arm/helper.c +++ b/target-arm/helper.c @@ -6642,6 +6642,7 @@ static bool get_phys_addr_lpae(CPUARMState *env, target_ulong address, int ap, ns, xn, pxn; uint32_t el = regime_el(env, mmu_idx); bool ttbr1_valid = true; + uint64_t descaddrmask; /* TODO: * This code does not handle the different format TCR for VTCR_EL2. @@ -6831,6 +6832,15 @@ static bool get_phys_addr_lpae(CPUARMState *env, target_ulong address, descaddr = extract64(ttbr, 0, 48); descaddr &= ~((1ULL << (inputsize - (stride * (4 - level)))) - 1); + /* The address field in the descriptor goes up to bit 39 for ARMv7 + * but up to bit 47 for ARMv8. + */ + if (arm_feature(env, ARM_FEATURE_V8)) { + descaddrmask = 0xfffffffff000ULL; + } else { + descaddrmask = 0xfffffff000ULL; + } + /* Secure accesses start with the page table in secure memory and * can be downgraded to non-secure at any step. Non-secure accesses * remain non-secure. We implement this by just ORing in the NSTable/NS @@ -6854,7 +6864,7 @@ static bool get_phys_addr_lpae(CPUARMState *env, target_ulong address, /* Invalid, or the Reserved level 3 encoding */ goto do_fault; } - descaddr = descriptor & 0xfffffff000ULL; + descaddr = descriptor & descaddrmask; if ((descriptor & 2) && (level < 3)) { /* Table entry. The top five bits are attributes which may From e14f0eb12f920fd96b9f79d15cedd437648e8667 Mon Sep 17 00:00:00 2001 From: Peter Maydell Date: Tue, 24 Nov 2015 14:12:15 +0000 Subject: [PATCH 4/4] target-arm/translate-a64.c: Correct unallocated checks for ldst_excl The checks for the unallocated encodings in the ldst_excl group (exclusives and load-acquire/store-release) were not correct. This error meant that in turn we ended up with code attempting to handle the non-existent case of "non-exclusive load-acquire/store-release pair". Delete that broken and now unreachable code. Reported-by: Laurent Desnogues Signed-off-by: Peter Maydell Reviewed-by: Laurent Desnogues Reviewed-by: Edgar E. Iglesias Reviewed-by: Sergey Fedorov --- target-arm/translate-a64.c | 15 ++------------- 1 file changed, 2 insertions(+), 13 deletions(-) diff --git a/target-arm/translate-a64.c b/target-arm/translate-a64.c index fe485a457d..14e8131b05 100644 --- a/target-arm/translate-a64.c +++ b/target-arm/translate-a64.c @@ -1816,9 +1816,6 @@ static void gen_store_exclusive(DisasContext *s, int rd, int rt, int rt2, * o2: 0 -> exclusive, 1 -> not * o1: 0 -> single register, 1 -> register pair * o0: 1 -> load-acquire/store-release, 0 -> not - * - * o0 == 0 AND o2 == 1 is un-allocated - * o1 == 1 is un-allocated except for 32 and 64 bit sizes */ static void disas_ldst_excl(DisasContext *s, uint32_t insn) { @@ -1833,7 +1830,8 @@ static void disas_ldst_excl(DisasContext *s, uint32_t insn) int size = extract32(insn, 30, 2); TCGv_i64 tcg_addr; - if ((!is_excl && !is_lasr) || + if ((!is_excl && !is_pair && !is_lasr) || + (!is_excl && is_pair) || (is_pair && size < 2)) { unallocated_encoding(s); return; @@ -1862,15 +1860,6 @@ static void disas_ldst_excl(DisasContext *s, uint32_t insn) } else { do_gpr_ld(s, tcg_rt, tcg_addr, size, false, false); } - if (is_pair) { - TCGv_i64 tcg_rt2 = cpu_reg(s, rt); - tcg_gen_addi_i64(tcg_addr, tcg_addr, 1 << size); - if (is_store) { - do_gpr_st(s, tcg_rt2, tcg_addr, size); - } else { - do_gpr_ld(s, tcg_rt2, tcg_addr, size, false, false); - } - } } }