target/riscv: Split out the vill from vtype
We need not specially process vtype when XLEN changes. Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-id: 20220120122050.41546-16-zhiwei_liu@c-sky.com Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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@ -125,6 +125,7 @@ struct CPURISCVState {
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target_ulong vl;
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target_ulong vstart;
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target_ulong vtype;
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bool vill;
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target_ulong pc;
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target_ulong load_res;
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@ -60,8 +60,7 @@ void cpu_get_tb_cpu_state(CPURISCVState *env, target_ulong *pc,
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uint32_t maxsz = vlmax << sew;
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bool vl_eq_vlmax = (env->vstart == 0) && (vlmax == env->vl) &&
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(maxsz >= 8);
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flags = FIELD_DP32(flags, TB_FLAGS, VILL,
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FIELD_EX64(env->vtype, VTYPE, VILL));
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flags = FIELD_DP32(flags, TB_FLAGS, VILL, env->vill);
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flags = FIELD_DP32(flags, TB_FLAGS, SEW, sew);
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flags = FIELD_DP32(flags, TB_FLAGS, LMUL,
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FIELD_EX64(env->vtype, VTYPE, VLMUL));
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@ -283,7 +283,18 @@ static RISCVException write_fcsr(CPURISCVState *env, int csrno,
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static RISCVException read_vtype(CPURISCVState *env, int csrno,
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target_ulong *val)
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{
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*val = env->vtype;
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uint64_t vill;
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switch (env->xl) {
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case MXL_RV32:
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vill = (uint32_t)env->vill << 31;
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break;
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case MXL_RV64:
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vill = (uint64_t)env->vill << 63;
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break;
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default:
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g_assert_not_reached();
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}
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*val = (target_ulong)vill | env->vtype;
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return RISCV_EXCP_NONE;
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}
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@ -124,8 +124,8 @@ static bool vector_needed(void *opaque)
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static const VMStateDescription vmstate_vector = {
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.name = "cpu/vector",
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.version_id = 1,
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.minimum_version_id = 1,
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.version_id = 2,
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.minimum_version_id = 2,
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.needed = vector_needed,
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.fields = (VMStateField[]) {
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VMSTATE_UINT64_ARRAY(env.vreg, RISCVCPU, 32 * RV_VLEN_MAX / 64),
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@ -134,6 +134,7 @@ static const VMStateDescription vmstate_vector = {
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VMSTATE_UINTTL(env.vl, RISCVCPU),
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VMSTATE_UINTTL(env.vstart, RISCVCPU),
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VMSTATE_UINTTL(env.vtype, RISCVCPU),
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VMSTATE_BOOL(env.vill, RISCVCPU),
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VMSTATE_END_OF_LIST()
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}
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};
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@ -52,7 +52,8 @@ target_ulong HELPER(vsetvl)(CPURISCVState *env, target_ulong s1,
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|| (ediv != 0)
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|| (reserved != 0)) {
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/* only set vill bit. */
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env->vtype = FIELD_DP64(0, VTYPE, VILL, 1);
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env->vill = 1;
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env->vtype = 0;
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env->vl = 0;
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env->vstart = 0;
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return 0;
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