target-openrisc: Remove unnecessary code generated by jump instructions
The sr_f variable is only used for the l.bf and l.bnf instructions. For clarity the code is also rewritten using a switch statement instead of if chaining. Signed-off-by: Sebastian Macke <sebastian@macke.de> Reviewed-by: Jia Liu <proljc@gmail.com> Signed-off-by: Jia Liu <proljc@gmail.com>
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@ -209,42 +209,49 @@ static void gen_goto_tb(DisasContext *dc, int n, target_ulong dest)
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static void gen_jump(DisasContext *dc, uint32_t imm, uint32_t reg, uint32_t op0)
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{
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target_ulong tmp_pc;
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int lab = gen_new_label();
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TCGv sr_f = tcg_temp_new();
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/* N26, 26bits imm */
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tmp_pc = sign_extend((imm<<2), 26) + dc->pc;
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tcg_gen_andi_tl(sr_f, cpu_sr, SR_F);
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if (op0 == 0x00) { /* l.j */
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switch (op0) {
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case 0x00: /* l.j */
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tcg_gen_movi_tl(jmp_pc, tmp_pc);
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} else if (op0 == 0x01) { /* l.jal */
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break;
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case 0x01: /* l.jal */
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tcg_gen_movi_tl(cpu_R[9], (dc->pc + 8));
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tcg_gen_movi_tl(jmp_pc, tmp_pc);
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} else if (op0 == 0x03) { /* l.bnf */
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break;
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case 0x03: /* l.bnf */
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case 0x04: /* l.bf */
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{
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int lab = gen_new_label();
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TCGv sr_f = tcg_temp_new();
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tcg_gen_movi_tl(jmp_pc, dc->pc+8);
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tcg_gen_brcondi_i32(TCG_COND_EQ, sr_f, SR_F, lab);
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tcg_gen_andi_tl(sr_f, cpu_sr, SR_F);
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tcg_gen_brcondi_i32(op0 == 0x03 ? TCG_COND_EQ : TCG_COND_NE,
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sr_f, SR_F, lab);
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tcg_gen_movi_tl(jmp_pc, tmp_pc);
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gen_set_label(lab);
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} else if (op0 == 0x04) { /* l.bf */
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tcg_gen_movi_tl(jmp_pc, dc->pc+8);
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tcg_gen_brcondi_i32(TCG_COND_NE, sr_f, SR_F, lab);
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tcg_gen_movi_tl(jmp_pc, tmp_pc);
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gen_set_label(lab);
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} else if (op0 == 0x11) { /* l.jr */
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tcg_temp_free(sr_f);
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}
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break;
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case 0x11: /* l.jr */
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tcg_gen_mov_tl(jmp_pc, cpu_R[reg]);
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} else if (op0 == 0x12) { /* l.jalr */
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break;
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case 0x12: /* l.jalr */
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tcg_gen_movi_tl(cpu_R[9], (dc->pc + 8));
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tcg_gen_mov_tl(jmp_pc, cpu_R[reg]);
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} else {
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break;
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default:
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gen_illegal_exception(dc);
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break;
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}
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tcg_temp_free(sr_f);
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dc->delayed_branch = 2;
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dc->tb_flags |= D_FLAG;
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gen_sync_flags(dc);
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}
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static void dec_calc(DisasContext *dc, uint32_t insn)
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{
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uint32_t op0, op1, op2;
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