From da61f1256f55a5e9fc03f7c88e3caa425d6bf8cf Mon Sep 17 00:00:00 2001 From: Frank Chang Date: Tue, 18 Jan 2022 09:45:15 +0800 Subject: [PATCH] target/riscv: rvv-1.0: Add Zve32f support for configuration insns All Zve* extensions support the vector configuration instructions. Signed-off-by: Frank Chang Reviewed-by: Alistair Francis Message-id: 20220118014522.13613-13-frank.chang@sifive.com Signed-off-by: Alistair Francis --- target/riscv/insn_trans/trans_rvv.c.inc | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc index 9fa3862620..fd6e74c232 100644 --- a/target/riscv/insn_trans/trans_rvv.c.inc +++ b/target/riscv/insn_trans/trans_rvv.c.inc @@ -152,7 +152,7 @@ static bool do_vsetvl(DisasContext *s, int rd, int rs1, TCGv s2) TCGv s1, dst; if (!require_rvv(s) || - !(has_ext(s, RVV) || s->ext_zve64f)) { + !(has_ext(s, RVV) || s->ext_zve32f || s->ext_zve64f)) { return false; } @@ -188,7 +188,7 @@ static bool do_vsetivli(DisasContext *s, int rd, TCGv s1, TCGv s2) TCGv dst; if (!require_rvv(s) || - !(has_ext(s, RVV) || s->ext_zve64f)) { + !(has_ext(s, RVV) || s->ext_zve32f || s->ext_zve64f)) { return false; }