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Bugfix in PowerPC dcbi instruction: 

we must do a load before the store, or we'll store random data.
Update cache instructions comments.


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3448 c046a42c-6fe2-441c-8c8c-71466251a162
This commit is contained in:
j_mayer 2007-10-26 00:48:00 +00:00
parent c7697e1f51
commit dac454af57
1 changed files with 2 additions and 5 deletions
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7
target-ppc/translate.c
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@ -3618,13 +3618,10 @@ GEN_HANDLER(mtspr, 0x1F, 0x13, 0x0E, 0x00000001, PPC_MISC)
}
/*** Cache management ***/
/* For now, all those will be implemented as nop:
* this is valid, regarding the PowerPC specs...
* We just have to flush tb while invalidating instruction cache lines...
*/
/* dcbf */
GEN_HANDLER(dcbf, 0x1F, 0x16, 0x02, 0x03C00001, PPC_CACHE)
{
/* XXX: specification says this is treated as a load by the MMU */
gen_addr_reg_index(ctx);
op_ldst(lbz);
}
@ -3641,7 +3638,7 @@ GEN_HANDLER(dcbi, 0x1F, 0x16, 0x0E, 0x03E00001, PPC_CACHE)
}
gen_addr_reg_index(ctx);
/* XXX: specification says this should be treated as a store by the MMU */
//op_ldst(lbz);
op_ldst(lbz);
op_ldst(stb);
#endif
}