tcg/loongarch64: Implement tcg_out_mov and tcg_out_movi
Signed-off-by: WANG Xuerui <git@xen0n.name> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20211221054105.178795-10-git@xen0n.name> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
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@ -247,6 +247,141 @@ static void tcg_out_mb(TCGContext *s, TCGArg a0)
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tcg_out_opc_dbar(s, 0);
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}
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static bool tcg_out_mov(TCGContext *s, TCGType type, TCGReg ret, TCGReg arg)
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{
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if (ret == arg) {
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return true;
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}
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switch (type) {
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case TCG_TYPE_I32:
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case TCG_TYPE_I64:
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/*
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* Conventional register-register move used in LoongArch is
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* `or dst, src, zero`.
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*/
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tcg_out_opc_or(s, ret, arg, TCG_REG_ZERO);
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break;
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default:
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g_assert_not_reached();
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}
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return true;
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}
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static bool imm_part_needs_loading(bool high_bits_are_ones,
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tcg_target_long part)
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{
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if (high_bits_are_ones) {
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return part != -1;
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} else {
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return part != 0;
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}
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}
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/* Loads a 32-bit immediate into rd, sign-extended. */
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static void tcg_out_movi_i32(TCGContext *s, TCGReg rd, int32_t val)
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{
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tcg_target_long lo = sextreg(val, 0, 12);
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tcg_target_long hi12 = sextreg(val, 12, 20);
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/* Single-instruction cases. */
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if (lo == val) {
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/* val fits in simm12: addi.w rd, zero, val */
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tcg_out_opc_addi_w(s, rd, TCG_REG_ZERO, val);
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return;
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}
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if (0x800 <= val && val <= 0xfff) {
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/* val fits in uimm12: ori rd, zero, val */
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tcg_out_opc_ori(s, rd, TCG_REG_ZERO, val);
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return;
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}
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/* High bits must be set; load with lu12i.w + optional ori. */
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tcg_out_opc_lu12i_w(s, rd, hi12);
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if (lo != 0) {
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tcg_out_opc_ori(s, rd, rd, lo & 0xfff);
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}
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}
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static void tcg_out_movi(TCGContext *s, TCGType type, TCGReg rd,
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tcg_target_long val)
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{
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/*
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* LoongArch conventionally loads 64-bit immediates in at most 4 steps,
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* with dedicated instructions for filling the respective bitfields
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* below:
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*
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* 6 5 4 3
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* 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2
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* +-----------------------+---------------------------------------+...
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* | hi52 | hi32 |
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* +-----------------------+---------------------------------------+...
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* 3 2 1
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* 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
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* ...+-------------------------------------+-------------------------+
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* | hi12 | lo |
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* ...+-------------------------------------+-------------------------+
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*
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* Check if val belong to one of the several fast cases, before falling
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* back to the slow path.
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*/
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intptr_t pc_offset;
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tcg_target_long val_lo, val_hi, pc_hi, offset_hi;
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tcg_target_long hi32, hi52;
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bool rd_high_bits_are_ones;
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/* Value fits in signed i32. */
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if (type == TCG_TYPE_I32 || val == (int32_t)val) {
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tcg_out_movi_i32(s, rd, val);
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return;
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}
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/* PC-relative cases. */
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pc_offset = tcg_pcrel_diff(s, (void *)val);
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if (pc_offset == sextreg(pc_offset, 0, 22) && (pc_offset & 3) == 0) {
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/* Single pcaddu2i. */
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tcg_out_opc_pcaddu2i(s, rd, pc_offset >> 2);
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return;
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}
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if (pc_offset == (int32_t)pc_offset) {
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/* Offset within 32 bits; load with pcalau12i + ori. */
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val_lo = sextreg(val, 0, 12);
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val_hi = val >> 12;
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pc_hi = (val - pc_offset) >> 12;
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offset_hi = val_hi - pc_hi;
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tcg_debug_assert(offset_hi == sextreg(offset_hi, 0, 20));
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tcg_out_opc_pcalau12i(s, rd, offset_hi);
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if (val_lo != 0) {
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tcg_out_opc_ori(s, rd, rd, val_lo & 0xfff);
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}
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return;
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}
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hi32 = sextreg(val, 32, 20);
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hi52 = sextreg(val, 52, 12);
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/* Single cu52i.d case. */
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if (ctz64(val) >= 52) {
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tcg_out_opc_cu52i_d(s, rd, TCG_REG_ZERO, hi52);
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return;
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}
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/* Slow path. Initialize the low 32 bits, then concat high bits. */
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tcg_out_movi_i32(s, rd, val);
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rd_high_bits_are_ones = (int32_t)val < 0;
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if (imm_part_needs_loading(rd_high_bits_are_ones, hi32)) {
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tcg_out_opc_cu32i_d(s, rd, hi32);
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rd_high_bits_are_ones = hi32 < 0;
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}
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if (imm_part_needs_loading(rd_high_bits_are_ones, hi52)) {
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tcg_out_opc_cu52i_d(s, rd, rd, hi52);
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}
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}
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/*
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* Entry-points
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*/
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@ -262,6 +397,8 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc,
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tcg_out_mb(s, a0);
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break;
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case INDEX_op_mov_i32: /* Always emitted via tcg_out_mov. */
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case INDEX_op_mov_i64:
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default:
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g_assert_not_reached();
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}
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