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target-alpha: Reduce internal processor registers for user-mode.

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The existing set of IPRs is totally irrelevant to user-mode emulation.
Indeed, they most are irrelevant to implementing kernel-mode emulation,
and would only be relevant to PAL-mode emulation, which I suspect that
no one will ever attempt.

Reducing the set of processor registers reduces the size of the CPU state.

Signed-off-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
This commit is contained in:
Richard Henderson 2010-01-04 11:19:14 -08:00 committed by Aurelien Jarno
parent 8443effb50
commit dad081ee69
3 changed files with 34 additions and 21 deletions
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4
linux-user/main.c
View File

@ -3054,10 +3054,8 @@ int main(int argc, char **argv, char **envp)
for(i = 0; i < 28; i++) {
env->ir[i] = ((abi_ulong *)regs)[i];
}
env->ipr[IPR_USP] = regs->usp;
env->ir[30] = regs->usp;
env->ir[IR_SP] = regs->usp;
env->pc = regs->pc;
env->unique = regs->unique;
}
#elif defined(TARGET_CRIS)
{

6
target-alpha/cpu.h
View File

@ -193,6 +193,11 @@ enum {
/* Internal processor registers */
/* XXX: TOFIX: most of those registers are implementation dependant */
enum {
#if defined(CONFIG_USER_ONLY)
IPR_EXC_ADDR,
IPR_EXC_SUM,
IPR_EXC_MASK,
#else
/* Ebox IPRs */
IPR_CC = 0xC0, /* 21264 */
IPR_CC_CTL = 0xC1, /* 21264 */
@ -306,6 +311,7 @@ enum {
IPR_VPTB,
IPR_WHAMI,
IPR_ALT_MODE,
#endif
IPR_LAST,
};

45
target-alpha/translate.c
View File

@ -2721,7 +2721,6 @@ static const struct cpu_def_t cpu_defs[] = {
CPUAlphaState * cpu_alpha_init (const char *cpu_model)
{
CPUAlphaState *env;
uint64_t hwpcb;
int implver, amask, i, max;
env = qemu_mallocz(sizeof(CPUAlphaState));
@ -2752,24 +2751,34 @@ CPUAlphaState * cpu_alpha_init (const char *cpu_model)
| FPCR_UNFD | FPCR_INED | FPCR_DNOD));
#endif
pal_init(env);
/* Initialize IPR */
hwpcb = env->ipr[IPR_PCBB];
env->ipr[IPR_ASN] = 0;
env->ipr[IPR_ASTEN] = 0;
env->ipr[IPR_ASTSR] = 0;
env->ipr[IPR_DATFX] = 0;
/* XXX: fix this */
// env->ipr[IPR_ESP] = ldq_raw(hwpcb + 8);
// env->ipr[IPR_KSP] = ldq_raw(hwpcb + 0);
// env->ipr[IPR_SSP] = ldq_raw(hwpcb + 16);
// env->ipr[IPR_USP] = ldq_raw(hwpcb + 24);
env->ipr[IPR_FEN] = 0;
env->ipr[IPR_IPL] = 31;
env->ipr[IPR_MCES] = 0;
env->ipr[IPR_PERFMON] = 0; /* Implementation specific */
// env->ipr[IPR_PTBR] = ldq_raw(hwpcb + 32);
env->ipr[IPR_SISR] = 0;
env->ipr[IPR_VIRBND] = -1ULL;
#if defined (CONFIG_USER_ONLY)
env->ipr[IPR_EXC_ADDR] = 0;
env->ipr[IPR_EXC_SUM] = 0;
env->ipr[IPR_EXC_MASK] = 0;
#else
{
uint64_t hwpcb;
hwpcb = env->ipr[IPR_PCBB];
env->ipr[IPR_ASN] = 0;
env->ipr[IPR_ASTEN] = 0;
env->ipr[IPR_ASTSR] = 0;
env->ipr[IPR_DATFX] = 0;
/* XXX: fix this */
// env->ipr[IPR_ESP] = ldq_raw(hwpcb + 8);
// env->ipr[IPR_KSP] = ldq_raw(hwpcb + 0);
// env->ipr[IPR_SSP] = ldq_raw(hwpcb + 16);
// env->ipr[IPR_USP] = ldq_raw(hwpcb + 24);
env->ipr[IPR_FEN] = 0;
env->ipr[IPR_IPL] = 31;
env->ipr[IPR_MCES] = 0;
env->ipr[IPR_PERFMON] = 0; /* Implementation specific */
// env->ipr[IPR_PTBR] = ldq_raw(hwpcb + 32);
env->ipr[IPR_SISR] = 0;
env->ipr[IPR_VIRBND] = -1ULL;
}
#endif
qemu_init_vcpu(env);
return env;