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target/mips: implement Octeon-specific arithmetic instructions 

This patch implements several Octeon-specific instructions:
- BADDU
- DMUL
- EXTS/EXTS32
- CINS/CINS32
- POP/DPOP
- SEQ/SEQI
- SNE/SNEI

Signed-off-by: Pavel Dovgalyuk <Pavel.Dovgalyuk@ispras.ru>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <165572673245.167724.17377788816335619000.stgit@pasha-ThinkPad-X280>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
This commit is contained in:
Pavel Dovgalyuk 2022-06-20 15:05:32 +03:00 committed by Philippe Mathieu-Daudé
parent 5e806fb002
commit dadd071a9c
2 changed files with 181 additions and 0 deletions
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26
target/mips/tcg/octeon.decode
View File

@ -13,3 +13,29 @@
%bbit_p 28:1 16:5
BBIT 11 set:1 . 10 rs:5 ..... offset:16 p=%bbit_p
# Arithmetic
# BADDU rd, rs, rt
# DMUL rd, rs, rt
# EXTS rt, rs, p, lenm1
# EXTS32 rt, rs, p, lenm1
# CINS rt, rs, p, lenm1
# CINS32 rt, rs, p, lenm1
# DPOP rd, rs
# POP rd, rs
# SEQ rd, rs, rt
# SEQI rt, rs, immediate
# SNE rd, rs, rt
# SNEI rt, rs, immediate
@r3 ...... rs:5 rt:5 rd:5 ..... ......
%bitfield_p 0:1 6:5
@bitfield ...... rs:5 rt:5 lenm1:5 ..... ..... . p=%bitfield_p
BADDU 011100 ..... ..... ..... 00000 101000 @r3
DMUL 011100 ..... ..... ..... 00000 000011 @r3
EXTS 011100 ..... ..... ..... ..... 11101 . @bitfield
CINS 011100 ..... ..... ..... ..... 11001 . @bitfield
POP 011100 rs:5 00000 rd:5 00000 10110 dw:1
SEQNE 011100 rs:5 rt:5 rd:5 00000 10101 ne:1
SEQNEI 011100 rs:5 rt:5 imm:s10 10111 ne:1

155
target/mips/tcg/octeon_translate.c
View File

@ -44,3 +44,158 @@ static bool trans_BBIT(DisasContext *ctx, arg_BBIT *a)
tcg_temp_free(t0);
return true;
}
static bool trans_BADDU(DisasContext *ctx, arg_BADDU *a)
{
TCGv t0, t1;
if (a->rt == 0) {
/* nop */
return true;
}
t0 = tcg_temp_new();
t1 = tcg_temp_new();
gen_load_gpr(t0, a->rs);
gen_load_gpr(t1, a->rt);
tcg_gen_add_tl(t0, t0, t1);
tcg_gen_andi_i64(cpu_gpr[a->rd], t0, 0xff);
tcg_temp_free(t0);
tcg_temp_free(t1);
return true;
}
static bool trans_DMUL(DisasContext *ctx, arg_DMUL *a)
{
TCGv t0, t1;
if (a->rt == 0) {
/* nop */
return true;
}
t0 = tcg_temp_new();
t1 = tcg_temp_new();
gen_load_gpr(t0, a->rs);
gen_load_gpr(t1, a->rt);
tcg_gen_mul_i64(cpu_gpr[a->rd], t0, t1);
tcg_temp_free(t0);
tcg_temp_free(t1);
return true;
}
static bool trans_EXTS(DisasContext *ctx, arg_EXTS *a)
{
TCGv t0;
if (a->rt == 0) {
/* nop */
return true;
}
t0 = tcg_temp_new();
gen_load_gpr(t0, a->rs);
tcg_gen_sextract_tl(t0, t0, a->p, a->lenm1 + 1);
gen_store_gpr(t0, a->rt);
tcg_temp_free(t0);
return true;
}
static bool trans_CINS(DisasContext *ctx, arg_CINS *a)
{
TCGv t0;
if (a->rt == 0) {
/* nop */
return true;
}
t0 = tcg_temp_new();
gen_load_gpr(t0, a->rs);
tcg_gen_deposit_z_tl(t0, t0, a->p, a->lenm1 + 1);
gen_store_gpr(t0, a->rt);
tcg_temp_free(t0);
return true;
}
static bool trans_POP(DisasContext *ctx, arg_POP *a)
{
TCGv t0;
if (a->rd == 0) {
/* nop */
return true;
}
t0 = tcg_temp_new();
gen_load_gpr(t0, a->rs);
if (!a->dw) {
tcg_gen_andi_i64(t0, t0, 0xffffffff);
}
tcg_gen_ctpop_tl(t0, t0);
gen_store_gpr(t0, a->rd);
tcg_temp_free(t0);
return true;
}
static bool trans_SEQNE(DisasContext *ctx, arg_SEQNE *a)
{
TCGv t0, t1;
if (a->rd == 0) {
/* nop */
return true;
}
t0 = tcg_temp_new();
t1 = tcg_temp_new();
gen_load_gpr(t0, a->rs);
gen_load_gpr(t1, a->rt);
if (a->ne) {
tcg_gen_setcond_tl(TCG_COND_NE, cpu_gpr[a->rd], t1, t0);
} else {
tcg_gen_setcond_tl(TCG_COND_EQ, cpu_gpr[a->rd], t1, t0);
}
tcg_temp_free(t0);
tcg_temp_free(t1);
return true;
}
static bool trans_SEQNEI(DisasContext *ctx, arg_SEQNEI *a)
{
TCGv t0;
if (a->rt == 0) {
/* nop */
return true;
}
t0 = tcg_temp_new();
gen_load_gpr(t0, a->rs);
/* Sign-extend to 64 bit value */
target_ulong imm = a->imm;
if (a->ne) {
tcg_gen_setcondi_tl(TCG_COND_NE, cpu_gpr[a->rt], t0, imm);
} else {
tcg_gen_setcondi_tl(TCG_COND_EQ, cpu_gpr[a->rt], t0, imm);
}
tcg_temp_free(t0);
return true;
}